Measurement of Branching Fractions and Charge Asymmetries

B Aubert, D Boutigny, JM Gaillard, A Hicheur… - Physical review …, 2002 - APS
The branching fractions of the exclusive decays B 0→ K* 0 γ and B+→ K*+ γ are measured
from a sample of (22.74±0.36)× 10 6 BB decays collected with the BABAR detector at the …

Methodology for 3-D substrate network extraction for spice simulation of parasitic currents in smart power ICs

P Buccella, C Stefanucci, H Zou… - … on Computer-Aided …, 2015 - ieeexplore.ieee.org
A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to
minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction …

A robust smart power bandgap reference circuit for use in an automotive environment

W Horn, H Zitta - IEEE Journal of Solid-State Circuits, 2002 - ieeexplore.ieee.org
In junction-isolated smart power technologies, negative voltages at the drain terminal of a
power DMOS lead to minority carrier injection into the substrate. This can cause malfunction …

[PDF][PDF] Substrate current effects in smart power ICs

M Schenkel - 2003 - research-collection.ethz.ch
MIKROELEKTRONIK+ INTEGRIERTE SCHALTUNGEN; LAYOUTS/MIKROELEKTRONIK;
DOPPELT DIFFUNDIERTE TRANSISTOREN, DMOS (ELEKTRONIK); CHIPS+ …

Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring

S Gupta, JC Beckman, SL Kosier - IEEE Electron Device …, 2001 - ieeexplore.ieee.org
The performance of the unbiased guard ring structure is measured and the effects of high
current, emitter area, and layout of unbiased guard rings are reported and explained …

[图书][B] ESD: design and synthesis

SH Voldman - 2011 - books.google.com
Electrostatic discharge (ESD) continues to impact semiconductor components and systems
as technologies scale from micro-to nano-electronics. This book studies electrical …

A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications

H Fujii, S Tokumitsu, T Mori… - … Devices and IC's …, 2017 - ieeexplore.ieee.org
This paper proposes a 90nm bulk BiCDMOS platform for automotive applications. In this
platform, two types of characteristic deep trench isolations are introduced. One has a top-to …

Latch-up characterization and checking of a 55 nm CMOS mixed voltage design

A Oberoi, M Khazhinsky, J Smith… - Electrical Overstress …, 2012 - ieeexplore.ieee.org
Mixed Voltage Design has become predominant in the semiconductor industry due to the
integration of high voltage and low voltage circuits in the pad ring. Latch-up characterization …

Analysis and modeling of minority carrier injection in deep-trench based BCD technologies

M Kollmitzer, M Olbrich, E Barke - Proceedings of the 2013 9th …, 2013 - ieeexplore.ieee.org
This paper proposes a methodology for circuit simulation of parasitic effects caused by
minority carrier injection into the substrate of a deep-trench based BCD technology. An …

Simulation, analysis, and verification of substrate currents for layout optimization of smart power ICs

P Buccella, C Stefanucci, JM Sallese… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed
during the circuit design phase. The state-of-the-art guidelines for the optimization of …