Low-cost memory fault tolerance for IoT devices

M Gottscho, I Alam, C Schoeny, L Dolecek… - ACM Transactions on …, 2017 - dl.acm.org
IoT devices need reliable hardware at low cost. It is challenging to efficiently cope with both
hard and soft faults in embedded scratchpad memories. To address this problem, we …

[图书][B] Lightweight Opportunistic Memory Resilience

I Alam - 2021 - search.proquest.com
The reliability of memory subsystems is worsening rapidly and needs to be considered as
one of the primary design objectives when designing today's computer systems. From on …

Enabling efficient sub-block disabled caches using coarse grain spatial predictions

M Mavropoulos, G Keramidas, D Nikolos - Microprocessors and …, 2022 - Elsevier
Reducing the supply voltage in today′ s process technologies introduces significant
reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance …

Improving the Performance Predictability of Faulty Data Caches

M Mavropoulos, G Keramidas… - 2024 19th European …, 2024 - ieeexplore.ieee.org
The aggressive reduction of the supply voltage, aiming for ultra-low power operation, affects
the reliability of ICs and especially the memory structures (SRAM cells). Furthermore, the …

[图书][B] Opportunistic memory systems in presence of hardware variability

MW Gottscho - 2017 - search.proquest.com
The memory system presents many problems in computer architecture and system design.
An important challenge is worsening hardware variability that is caused by nanometer-scale …

Recovery of performance degradation in defective branch target buffers

F Filippou, G Keramidas… - 2016 IEEE 22nd …, 2016 - ieeexplore.ieee.org
Dynamic voltage and frequency scaling (DVFS) is a commonly-used power-management
technique. Unfortunately, voltage scaling increases the impact of process variations on …

Run Time Management of Faulty Data Caches

M Mavropoulos, G Keramidas… - 2021 IEEE European …, 2021 - ieeexplore.ieee.org
As the technology continuous to shrink, power consumption appears to be the main design
parameter. Operation on low voltage negatively affects mainly the operation of on-chip …

A novel fault tolerant cache architecture based on orthogonal latin squares theory

F Filippou, G Keramidas… - … Design, Automation & …, 2018 - ieeexplore.ieee.org
Aggressive dynamic voltage and frequency scaling is widely used to reduce the power
consumption of microprocessors. Unfortunately, voltage scaling increases the impact of …

Use Them-Don't Waste Them. Recruiting Strong ECC in L1 Caches for Hard Error Recovery Without the Penalty

M Mavropoulos, T Lappas, G Keramidas… - 11th European …, 2015 - hal.science
Operating below nominal voltage levels is a promising direction to enable ultra-low power
CMOS-based sytems. This is true due to the cubic relation between the dynamic power …

Performance Degrading Faults in Branch Target Buffers and Branch Predictors: Exploration and Remedy

F Filippou, G Keramidas, M Mavropoulos… - Available at SSRN … - papers.ssrn.com
Voltage scaling increases the impact of process variations resulting in an exponential ramp-
up in the number of malfunctioning SRAM cells. Our experimental findings reveal that for …