Since the CMOS technology scaling has focused on improving digital circuit, the design of
conventional analog circuits has become more and more difficult. To overcome this …

A scalable 64-lane chip-to-chip I/O, with per-lane data rate of 2-16 Gb/s is demonstrated in
32-nm low-power CMOS technology. At maximum aggregate bandwidth of 1.024 Tb/s …

This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …

Demand for increasing performance is far outpacing the capability of traditional methods for
performance scaling. Disruptive solutions are needed to advance beyond incremental …

A source-synchronous I/O architecture is reported that includes redundant receiver lanes to
enable lane recalibration with reduced power and area overhead. Key features and …

A wide range of memory configurations exist in today's high-speed digital systems to meet
platform-specific bandwidth, power, capacity, and cost constraints. In the near term, DDR4 …

This article presents a 25-Gb/s single-ended four-level pulse-amplitude modulation (PAM-4)
receiver with a time-windowed least significant bit (LSB) decoder for high-speed memory …

A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with
up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a …

This paper proposes the first feed-forward equalizing transmitter (Tx) which adaptively
relaxes impedance matching. Using an on-chip time-domain reflectometer monitor, the Tx …

This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-
VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is …