Sata: Sparsity-aware training accelerator for spiking neural networks

R Yin, A Moitra, A Bhattacharjee, Y Kim… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Spiking neural networks (SNNs) have gained huge attention as a potential energy-efficient
alternative to conventional artificial neural networks (ANNs) due to their inherent high …

Scale-out systolic arrays

AC Yüzügüler, C Sönmez, M Drumond, Y Oh… - ACM Transactions on …, 2023 - dl.acm.org
Multi-pod systolic arrays are emerging as the architecture of choice in DNN inference
accelerators. Despite their potential, designing multi-pod systolic arrays to maximize …

Cambricon-u: A systolic random increment memory architecture for unary computing

H Guo, Y Zhao, Z Li, Y Hao, C Liu, X Song, X Li… - Proceedings of the 56th …, 2023 - dl.acm.org
Unary computing, whose arithmetics require only one logic gate, has enabled efficient DNN
processing, especially on strictly power-constrained devices. However, unary computing still …

Efficient N: M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design

C Fang, W Sun, A Zhou, Z Wang - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Sparse training is one of the promising techniques to reduce the computational cost of deep
neural networks (DNNs) while retaining high accuracy. In particular, N: M fine-grained …

SC-CGRA: An Energy-Efficient CGRA Using Stochastic Computing

D Mou, B Wang, D Liu - IEEE Transactions on Parallel and …, 2024 - ieeexplore.ieee.org
Stochastic Computing (SC) offers a promising computing paradigm for low-power and cost-
effective applications, with the added advantage of high error tolerance. In parallel, Coarse …

Chameleon: Dual memory replay for online continual learning on edge devices

S Aggarwal, K Binici, T Mitra - IEEE Transactions on Computer …, 2023 - ieeexplore.ieee.org
Once deployed on edge devices, a deep neural network model should dynamically adapt to
newly discovered environments and personalize its utility for each user. The system must be …

Low-Precision Mixed-Computation Models for Inference on Edge

S Azizi, M Nazemi, M Kamal, M Pedram - IEEE Transactions on Very …, 2024 - computer.org
This article presents a mixed-computation neural network processing approach for edge
applications that incorporates low-precision (low-width) Posit and low-precision fixed point …

BiRD: Bi-directional Input Reuse Dataflow for Enhancing Depthwise Convolution Performance on Systolic Arrays

M Park, S Hwang, H Cho - IEEE Transactions on Computers, 2024 - ieeexplore.ieee.org
Depthwise convolution (DWConv) is an effective technique for reducing the size and
computational requirements of convolutional neural networks. However, DWConv's input …

ReDas: Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array

M Han, L Wang, L Xiao, T Cai, Z Wang, X Xu… - arXiv preprint arXiv …, 2023 - arxiv.org
Current systolic arrays still suffer from low performance and PE utilization on many real
workloads due to the mismatch between the fixed array topology and diverse DNN kernels …

Efficient Parallel Stochastic Computing Multiply-Accumulate (MAC) Technique Using Pseudo-Sobol Bit-Streams

A Hu, W Li, D Lyu, G He - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Stochastic computing (SC) has emerged as a promising technique for reducing hardware
costs in various applications, particularly in multiply-accumulate (MAC) intensive tasks such …