[PDF][PDF] A comprehensive evaluation of direct and indirect network-on-chip topologies

M Baboli, NS Husin, MN Marsono - Proceedings of the 2014 …, 2014 - researchgate.net
Over the last few years, there has been dramatic need for developing multi-processors with
higher processing capability with area constraint. The interconnect topology for the …

Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC)

MA Khan, AQ Ansari - … on Emerging Trends in Networks and …, 2011 - ieeexplore.ieee.org
The conventional two-dimensional (2-D) integrated circuit (IC) has limited scope for floor
planning and therefore limits the performance improvements resulting from the Network-on …

[PDF][PDF] Integrating Resilient Tier N+ 1 Networks with Distributed Non-Recursive Cloud Model for Cyber-Physical Applications.

KC Okafor, OM Longe - KSII Transactions on Internet & …, 2022 - researchgate.net
Cyber-physical systems (CPS) have been growing exponentially due to improved
clouddatacenter infrastructure-as-a-service (CDIaaS). Incremental expandability …

An efficient tree-based topology for Network-on-Chip

MA Khan, AQ Ansari - 2011 World Congress on Information and …, 2011 - ieeexplore.ieee.org
Performance of the network is measured in the term of throughput. The throughput and
efficiency of interconnect depends on network parameters of the topology. Therefore …

Hybrid Approach for Discovering k-Hamiltonian Paths in a Torus-Enhanced Butterfly Interconnected Network

TMA Latifah - Journal of Hunan University Natural Sciences, 2023 - jonuns.com
The significance of interconnection networks extends beyond the semiconductor industry,
becoming integral to industrial engineering, particularly in the era of the Internet of Things …

Topologies and routing strategies in MPSoC

S Tyagi, MA Khan - International Journal of Embedded …, 2013 - inderscienceonline.com
The routing and topology has significant role to play in the design of multiprocessor system-
on-chip (MPSoC). The topology has impact on the performance of the routing algorithms. As …

[PDF][PDF] Torus embedded hypercube interconnection network: A comparative study

NG Kini, MS Kumar, HS Mruthyunjaya - International Journal of Computer …, 2010 - Citeseer
ABSTRACT A design analysis and comparison of a product network generated from torus
and hypercube networks known as torus embedded hypercube scalable interconnection …

[PDF][PDF] ANew INTERCONNECTION TOPOLOGY FOR NETWORK ON CHIP

L Tripathy, CR Tripathy - Int. J. Comput. Netw. Commun.(IJCNC), 2018 - academia.edu
The architecture of networks on chip (NOC) highly affects the overall performance of the
system on chip (SOC). A new topology for chip interconnection called Torus connected …

[图书][B] Multicore Technology: Architecture, Reconfiguration, and Modeling

MY Qadri, SJ Sangwine - 2018 - books.google.com
The saturation of design complexity and clock frequencies for single-core processors has
resulted in the emergence of multicore architectures as an alternative design paradigm …

[引用][C] 三维片上网络研究综述

张大坤, 黄翠, 宋国治 - 软件学报, 2015