Modulonet: Neural networks meet modular arithmetic for efficient hardware masking

A Dubey, A Ahmad, MA Pasha… - IACR Transactions on …, 2022 - tches.iacr.org
Intellectual Property (IP) thefts of trained machine learning (ML) models through side-
channel attacks on inference engines are becoming a major threat. Indeed, several recent …

Randomness generation for secure hardware masking-unrolled trivium to the rescue

G Cassiers, L Masure, C Momin, T Moos… - Cryptology ePrint …, 2023 - eprint.iacr.org
Masking is a prominent strategy to protect cryptographic implementations against side-
channel analysis. Its popularity arises from the exponential security gains that can be …

Securing AES designs against power analysis attacks: a survey

TB Singha, RP Palathinkal… - IEEE Internet of Things …, 2023 - ieeexplore.ieee.org
With the advent of Internet of Things (IoT), the call for hardware security has been seriously
demanding due to the risks of side-channel attacks from adversaries. Advanced encryption …

Riding the waves towards generic single-cycle masking in hardware

R Nagpal, B Gigerl, R Primas, S Mangard - Cryptology ePrint Archive, 2022 - eprint.iacr.org
Research on the design of masked cryptographic hardware circuits in the past has mostly
focused on reducing area and randomness requirements. However, many embedded …

WAGE: an authenticated encryption with a twist

R AlTawy, G Gong, K Mandal, R Rohit - IACR Transactions on …, 2020 - tosc.iacr.org
This paper presents WAGE, a new lightweight sponge-based authenticated cipher whose
underlying permutation is based on a 37-stage Galois NLFSR over F 2 7. At its core, the …

Circuit masking: from theory to standardization, a comprehensive survey for hardware security researchers and practitioners

A Covic, F Ganji, D Forte - arXiv preprint arXiv:2106.12714, 2021 - arxiv.org
Side-channel attacks extracting sensitive data from implementations have been considered
a major threat to the security of cryptographic schemes. This has elevated the need for …

Bake It Till You Make It: Heat-induced Power Leakage from Masked Neural Networks

DM Mehta, M Hashemi, DS Koblah, D Forte… - Cryptology ePrint …, 2023 - eprint.iacr.org
Masking has become one of the most effective approaches for securing hardware designs
against side-channel attacks. Regardless of the effort put into correctly implementing …

A low-randomness second-order masked AES

T Beyne, S Dhooghe, A Ranea, D Šijačić - International Conference on …, 2021 - Springer
We propose a second-order masking of the AES in hardware that requires an order of
magnitude less random bits per encryption compared to previous work. The design and its …

Consolidating security notions in hardware masking

L De Meyer, B Bilgin, O Reparaz - IACR Transactions on …, 2019 - tches.iacr.org
In this paper, we revisit the security conditions of masked hardware implementations. We
describe a new, succinct, information-theoretic condition called d-glitch immunity which is …

Masking FALCON's Floating-Point Multiplication in Hardware

E Karabulut, A Aysu - IACR Transactions on Cryptographic Hardware …, 2024 - tches.iacr.org
Floating-point arithmetic is a cornerstone in a wide array of computational domains, and it
recently became a building block for the FALCON post-quantum digital signature algorithm …