A survey of optimization techniques for thermal-aware 3D processors

K Cao, J Zhou, T Wei, M Chen, S Hu, K Li - Journal of Systems Architecture, 2019 - Elsevier
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

A survey on mapping and scheduling techniques for 3D Network-on-chip

SP Kaur, M Ghose, A Pathak, R Patole - Journal of Systems Architecture, 2024 - Elsevier
Abstract Network-on-chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …

Throughput maximization for periodic real-time systems under the maximal temperature constraint

H Huang, V Chaturvedi, G Quan, J Fan… - ACM Transactions on …, 2014 - dl.acm.org
In this article, we study the problem of how to maximize the throughput of a periodic real-time
system under a given peak temperature constraint. We assume that different tasks in our …

An online thermal-constrained task scheduler for 3D multi-core processors

CH Liao, CHP Wen… - 2015 Design, Automation & …, 2015 - ieeexplore.ieee.org
Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely
impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to …

A fast high-level event-driven thermal estimator for dynamic thermal aware scheduling

J Cui, DL Maskell - … Transactions on Computer-Aided Design of …, 2012 - ieeexplore.ieee.org
Thermal aware scheduling (TAS) is an important system level optimization for many-core
systems. A fast event driven thermal estimation method, which includes both the dynamic …

Thermal-throttling server: A thermal-aware real-time task scheduling framework for three-dimensional multicore chips

TH Tsai, YS Chen - Journal of Systems and Software, 2016 - Elsevier
Abstract Three-dimensional (3D) multicore chips have been recently developed to deal with
the power consumption and interconnection delay problems of embedded systems; …

Thermal optimization in network-on-chip-based 3D chip multiprocessors using dynamic programming networks

N Dahir, R Al-Dujaily, T Mak, A Yakovlev - ACM Transactions on …, 2014 - dl.acm.org
The substantial silicon density in 3D VLSI, albeit its numerous advantages, introduces
serious thermal threats that would lead to faults and system failures. This article introduces a …

Thermal-constrained task scheduling on 3-D multicore processors for throughput-and-energy optimization

CH Liao, CHP Wen - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
Thermal-constrained task scheduler for throughput optimization on 3-D multicore processors
(3-D MCPs) has been studied extensively. However, these throughput-optimized strategies …

STEM: a thermal-constrained real-time scheduling for 3D heterogeneous-ISA multicore processors

TH Tsai, YS Chen, XX He, CY Li - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Synergistic processing between multiple instruction set architecture (ISA) cores and heat
flows in a 3D heterogeneous multicore chip exacerbates the complexity of thermal problems …

Thermal-aware task allocation, memory mapping, and task scheduling for 3D stacked memory and processor architecture

WK Cheng, TW Hsu - IEEE 2013 Tencon-Spring, 2013 - ieeexplore.ieee.org
Heterogeneous integration enabled by 3D technology is one of the innovations for future
microprocessor design. By the heterogeneous integration of memory and multi-core …