In this paper, we address an open problem of zero-shot learning. Its principle is based on
learning a mapping that associates feature vectors extracted from ie images and attribute …

Higher transistor counts, lower voltage levels, and reduced noise margin increase the
susceptibility of multicore processors to transient faults. Redundant hardware modules can …

The use of efficient synchronization mechanisms is crucial for implementing fine grained
parallel programs on modern shared cache multi-core architectures. In this paper we study …

Despite decades of innovation, existing hash tables fail to achieve peak performance on
modern hardware. Built around a relatively simple computation, ie, a hash function, which in …

Relentless technology scaling has made transistors more vulnerable to soft, or transient,
errors. To keep systems robust against these, current error detection techniques use …

Automatic parallelization is a promising approach to producing scalable multi-threaded
programs for multicore architectures. Many existing automatic techniques only parallelize …

Memory profiling captures programs' dynamic memory behavior, assisting programmers in
debugging, tuning, and enabling advanced compiler optimizations like speculation-based …

Data processing pipelines normally use lockless Single‐Producer–Single‐Consumer
(SPSC) queues to efficiently decouple their processing threads and achieve high …

Core-to-core communication is critical to the effective use of multi-core processors. A
number of software based concurrent lock-free queues have been proposed to address this …

In recent years, the number of CPU cores in a multi-core processor keeps increasing. To
leverage the increasing hardware resource, programmers need to develop parallelized …