An adaptive pre-distortion technique to mitigate the DTC nonlinearity in digital PLLs

S Levantino, G Marzin, C Samori - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in
the design of frequency synthesizers for wireless applications. However, the main obstacle …

A 3.6 GHz low-noise fractional-N digital PLL using SAR-ADC-based TDC

Z Xu, M Miyahara, K Okada… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band
phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to …

The rise of the digital RFIC era: An overview of past and present digital RFIC advancements

R Levinger, E Shumaker, R Banin… - IEEE Microwave …, 2022 - ieeexplore.ieee.org
It has been a mere 130 years since the first widely known wireless telegraphy apparatus
was demonstrated by Guglielmo Marconi, transmitting radio signals to a distance of about …

A 2.7 mW/channel 48–1000 MHz direct sampling full-band cable receiver

J Wu, G Cusmai, A Wei-Te Chou… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is
presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS …

A reconfigurable TAF-DPS frequency synthesizer on FPGA achieving 2 ppb frequency granularity and two-cycle switching speed

L Xiu, PL Chen - IEEE Transactions on Industrial Electronics, 2016 - ieeexplore.ieee.org
Frequency synthesizer is a key component used in electronic systems. Two important
features for judging its performance are frequency granularity and frequency switching …

A low-power and highly linear 14-bit parallel sampling TDC with power gating and DEM in 65-nm CMOS

S Liu, Y Zheng - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
This paper describes time-to-digital converter (TDC) architecture capable of achieving
subgate-delay resolution and large detection range at the same time with low power …

Learning with physical noise or errors

D Kamel, FX Standaert, A Duc… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Hard learning problems have recently attracted significant attention within the cryptographic
community, both as a versatile assumption on which to build various protocols, and as a …

Direct period synthesis for achieving sub-ppm frequency resolution through time average frequency: the principle, the experimental demonstration, and its application …

L Xiu - IEEE Transactions on Very Large Scale Integration …, 2014 - ieeexplore.ieee.org
Direct period synthesis is a technique of using a base time unit and the time-average-
frequency concept to synthesize clock frequency. Its distinguished capabilities include …

Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL)–a review

F Choong, MI Reaz, MI Kamaruzzaman… - Jurnal …, 2020 - researchportal.hw.ac.uk
Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage
control oscillator (VCO) with the advances of digital intensive research on all-digital phase …

Circuits and Techniques for All-Digital Frequency Synthesizers and Design Automation

K Kwon - 2023 - deepblue.lib.umich.edu
As semiconductor fabrication process become complex to achieve target yield and
performance in sub-20nm field-effect transistors (FETs), not only the number of design rule …