This paper presents a new transistor placement method applied to the ASTRAN EDA tool,
an open-source solution for the automatic design of complex digital gates. Although it …

The paper shows that minimal contact circuits are mapped into NCL gates with a minimal
number of transistors. To estimate the worst case of delays in the set and reset phases, the …

This paper presents an electrical study on logic functions with up to 4 inputs designed with a
standard cell mapping and two automatically generated supergates methodologies. The …

Recent developments in electronic design automation tools vastly reduce the design cost of
supergates, enabling an alternative approach to logic synthesis. Despite many design …

Custom standard cell libraries can improve the final quality of the corresponding VLSI
designs but properly customizing standard cell libraries remains challenging due to the …

The small number of logic functions in a traditional cell library limits the optimization of digital
design regarding transistors, wires, and vias count. It affects traditional quality metrics, like …

As the automated design of supergates becomes possible, techniques to improve their
electrical characteristics grow in relevance. Among the design choices, the order of …

In standard cell placement, a circuit is given consisting of cells with a standard
height,(different widths) and the problem is to place the cells in the standard rows of a chip …