Compiling for reconfigurable computing: A survey

JMP Cardoso, PC Diniz, M Weinhardt - ACM Computing Surveys (CSUR …, 2010 - dl.acm.org
Reconfigurable computing platforms offer the promise of substantially accelerating
computations through the concurrent nature of hardware structures and the ability of these …

[图书][B] Compilation techniques for reconfigurable architectures

JMP Cardoso, PC Diniz - 2011 - books.google.com
The extreme? exibility of recon? gurable architectures and their performance pot-tial have
made them a vehicle of choice in a wide range of computing domains, from rapid circuit …

Evolutionary multi-level acyclic graph partitioning

O Moreira, M Popp, C Schulz - Proceedings of the genetic and …, 2018 - dl.acm.org
Directed graphs are widely used to model data flow and execution dependencies in
streaming applications. This enables the utilization of graph partitioning algorithms for the …

Temporal partitioning data flow graphs for dynamically reconfigurable computing

YC Jiang, JF Wang - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
FPGA-based configurable computing machines are evolving rapidly in large signal
processing applications due to flexibility and high performance. In this paper, given a …

On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

JMP Cardoso - IEEE Transactions on Computers, 2003 - ieeexplore.ieee.org
Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration
capabilities, provides an attractive solution to save silicon area. Architectural synthesis for …

Search for a fermiophobic Higgs at LEP 2

P Abreu, W Adam, T Adye, P Adzic, I Ajinenko… - Physics Letters B, 2001 - Elsevier
Higgs bosons predicted by the fermiophobic scenario within Two Higgs Doublets Models
were searched for in the data collected by the DELPHI detector at centre-of-mass energies …

Novel algorithm combining temporal partitioning and sharing of functional units

JMP Cardoso - The 9th Annual IEEE Symposium on Field …, 2001 - ieeexplore.ieee.org
Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration
capabilities, provides an attractive solution to save silicon area. Architectural synthesis for …

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

O Lehtoranta, E Salminen, A Kulmala… - … Conference on Field …, 2005 - ieeexplore.ieee.org
A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip
(SoC) is presented. The goal is a computationally scalable framework independent of …

Run-time management of logic resources on reconfigurable systems

MG Gericota, GR Alves, ML Silva… - … , Automation and Test …, 2003 - ieeexplore.ieee.org
Dynamically reconfigurable systems based on partial and dynamically reconfigurable
FPGAs may have their functionality partially modified at run-time without stopping the …

An efficient list scheduling algorithm for time placement problem

A Mtibaa, B Ouni, M Abid - Computers & Electrical Engineering, 2007 - Elsevier
The partially reconfigurable FPGAs allows an overlap between the execution and the
reconfiguration of tasks. The partial approach can be used to fit a large application into the …