FinFET based SRAMs in Sub-10nm domain
An exponential rise in transistor count, have increased the power consumption of the
modern digital system. Moreover, at lower technology node, the performance of …
modern digital system. Moreover, at lower technology node, the performance of …
Nanosheet FET for Future Technology Scaling
AS Kumar, VB Sreenivasulu… - … Devices for Artificial …, 2024 - Wiley Online Library
Improvements in the VLSI industry have always been striving to justify the Moore's law by
implanting, twice count transistors from the existing one. This law has made a significant …
implanting, twice count transistors from the existing one. This law has made a significant …
A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry
MR Taheri, A Arasteh, S Mohammadyan… - Microprocessors and …, 2020 - Elsevier
Imprecising the arithmetic hardware blocks is well known as one of the brilliant approaches
that increase the performance of digital signal processors (DSP) at the cost of imposing …
that increase the performance of digital signal processors (DSP) at the cost of imposing …
Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM
In recent years, much emphasis is given for low power memory design by reducing leakage
power. Carbon nanotube field effect transistor (CNTFET) based static random access …
power. Carbon nanotube field effect transistor (CNTFET) based static random access …
Extended Gate to source overlap Heterojunction Vertical TFET: Design, analysis, and optimization with process parameter variations
This report highlights the simulated results of Extended gate to source overlap
Heterojunction Vertical Tunnel field effect transistor (EGH-VTFET) for low-power and high …
Heterojunction Vertical Tunnel field effect transistor (EGH-VTFET) for low-power and high …
Transmission gate‐based 9T SRAM cell for variation resilient low power and reliable internet of things applications
Higher variation resilience, lower power consumption, and higher reliability are the three
principal design metrics for designing a static random‐access memory (SRAM) cell. The …
principal design metrics for designing a static random‐access memory (SRAM) cell. The …
Design and development of efficient SRAM cell based on FinFET for low power memory applications
Stationary random‐access memory (SRAM) undergoes an expansion stage, to repel
advanced process variation and support ultra‐low power operation. Memories occupy more …
advanced process variation and support ultra‐low power operation. Memories occupy more …
Design and analysis of electrostatic doped tunnel CNTFET for various process parameters variation
In this paper, electrostatic doped Tunnel carbon nano tube field effect transistor (ED-Tunnel
CNTFET) is proposed. Additional gates in the source and drain regions draw an appropriate …
CNTFET) is proposed. Additional gates in the source and drain regions draw an appropriate …
Process evaluation in FinFET based 7T SRAM cell
TS Kumar, SL Tripathi - Analog Integrated Circuits and Signal Processing, 2021 - Springer
The main aim of device scaling or usage of different technology is to reduce power. The
major problem with technology scaling is power dissipation and stability of the device …
major problem with technology scaling is power dissipation and stability of the device …
Partially extended germanium source DG-TFET: design, analysis, and optimization for enhanced digital and analog/RF parameters
Tunnel field-effect transistors have demonstrated a predominant performance in the field of
semiconductors. However, low drive current and ambipolarity are major challenges for …
semiconductors. However, low drive current and ambipolarity are major challenges for …