Partial failure resilient memory management system for (cxl-based) distributed shared memory

M Zhang, T Ma, J Hua, Z Liu, K Chen, N Ding… - Proceedings of the 29th …, 2023 - dl.acm.org
The efficiency of distributed shared memory (DSM) has been greatly improved by recent
hardware technologies. But, the difficulty of distributed memory management can still be a …

An introduction to the compute express link (cxl) interconnect

DD Sharma, R Blankenship, DS Berger - arXiv preprint arXiv:2306.11227, 2023 - arxiv.org
The Compute Express Link (CXL) is an open industry-standard interconnect between
processors and devices such as accelerators, memory buffers, smart network interfaces …

Fabric-centric computing

M Liu - Proceedings of the 19th Workshop on Hot Topics in …, 2023 - dl.acm.org
Emerging memory fabrics and the resulting composable infrastructures have fundamentally
challenged our conventional wisdom on how to build efficient rack/cluster-scale systems …

Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL

Z Wang, Y Guo, K Lu, J Wan, D Wang, T Yao… - ACM Transactions on …, 2024 - dl.acm.org
Memory disaggregation is a promising architecture for modern datacenters that separates
compute and memory resources into independent pools connected by ultra-fast networks …

[PDF][PDF] Compiler-Directed Whole-System Persistence

J Zeng, T Zhang, C Jung - Proceedings of the 51th Annual …, 2024 - cs.purdue.edu
Nonvolatile memory (NVM) technologies have gained increasing attention thanks to their
density and durability benefits. However, leveraging NVM can cause a crash consistency …

REED: chiplet-based scalable hardware accelerator for fully homomorphic encryption

A Aikata, AC Mert, S Kwon, M Deryabin… - arXiv preprint arXiv …, 2023 - arxiv.org
Fully Homomorphic Encryption (FHE) has emerged as a promising technology for
processing encrypted data without the need for decryption. Despite its potential, its practical …

Logical Memory Pools: Flexible and Local Disaggregated Memory

E Amaro, S Wang, A Panda, MK Aguilera - Proceedings of the 22nd …, 2023 - dl.acm.org
We propose logical memory pools, a memory disaggregation architecture for the emerging
Compute Express Link (CXL) technology in datacenters. The key idea is to create a memory …

A case against cxl memory pooling

P Levis, K Lin, A Tai - Proceedings of the 22nd ACM Workshop on Hot …, 2023 - dl.acm.org
Compute Express Link (CXL) is a replacement for PCIe. With much lower latency than PCIe
and hardware support for cache coherence, programs can efficiently access remote memory …

A FPGA-based architecture for real-time cluster finding in the LHCb silicon pixel detector

G Bassi, L Giambastiani, K Hennessy… - … on Nuclear Science, 2023 - ieeexplore.ieee.org
This article describes a custom [very high speed integrated circuits (VHSIC) hardware
description language (VHDL)] firmware implementation of a 2-D cluster-finder architecture …

An Introduction to the Compute Express Link (CXL) Interconnect

D Das Sharma, R Blankenship, D Berger - ACM Computing Surveys, 2024 - dl.acm.org
The Compute Express Link (CXL) is an open industry-standard interconnect between
processors and devices such as accelerators, memory buffers, smart network interfaces …