6,009.261 6,094,695 6,185,629 6,189,088 6, 192466 6,308,255 6,334, 176 6,338,057
6,349,361 6,381,691 6,408,383 6,449,706 6.463, 582 6,499,116 6,513,109 6,570,511 …

Processing of character data is facilitated. A Find Element Not Equal instruction is provided
that compares data of multiple vectors for inequality and provides an indication of inequality …

Processing of character data is facilitated. A Find Element Equal instruction is provided that
compares data of multiple vectors for equality and provides an indication of equality, if …

Abstract A Vector Checksum instruction. Elements from a second operand are added
together one-by-one to obtain a first result. The adding includes performing one or more end …

Processing of character data is facilitated. A Vector String Range Compare instruction is
provided that compares each element of a vector with a range of values based on a set of …

Emulation of instructions that include non-contiguous specifiers is facilitated. A non-
contiguous specifier specifies a resource of an instruction, such as a register, using multiple …

5,222,225 5,410,661 5,495,592 5,497,468 5,551,013 5,574,873 5,608,887 5,790,825
5,812,147 5,931,940 6,009.261 6,094,695 6,185,629 6,189,088 6, 192466 6,308,255 6,334 …

Processing of character data is facilitated. A Find Element Equal instruction is provided that
compares data of multiple vectors for equality and provides an indication of equality, if …

(57) ABSTRACT A Load to Block Boundary instruction is provided that loads a variable
number of bytes of data into a register while ensuring that a specified memory boundary is …

(56) References Cited 2013/0246752 A1 9/2013 Bradbury et al. 2013, 0246753 A1 9/2013
Bradbury et al. US PATENT DOCUMENTS 2013, 0246757 A1 9/2013 Bradbury et al. 2013 …