Dynamic and partial reconfiguration of Zynq 7000 under Linux

M Al Kadi, P Rudolph, D Gohringer… - … Computing and FPGAs …, 2013 - ieeexplore.ieee.org
Dynamic and partial reconfiguration is a well-known technique to update the configuration of
a field programmable gate array (FPGA) at runtime. Xilinx FPGAs support this feature which …

Power consumption model for partial and dynamic reconfiguration

R Bonamy, D Chillet, S Bilavarn… - … Computing and FPGAs, 2012 - ieeexplore.ieee.org
In the context of embedded systems development, two important challenges are the efficient
use of silicon area and the energy consumption minimization. Hardware accelerated tasks …

Module relocation in heterogeneous reconfigurable systems-on-chip using the xilinx isolation design flow

L Gantel, MEA Benkhelifa… - 2012 International …, 2012 - ieeexplore.ieee.org
Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests,
heterogeneous processing elements in a single chip. Namely, several processors, hardware …

A reconfigurable framework for performance enhancement with dynamic FPGA configuration prefetching

A Lifa, P Eles, Z Peng - … Aided Design of Integrated Circuits and …, 2015 - ieeexplore.ieee.org
Many modern applications exhibit a dynamic and nonstationary behavior, with certain
characteristics in one phase of their execution, which change as the application enters new …

Power consumption models for the use of dynamic and partial reconfiguration

R Bonamy, S Bilavarn, D Chillet, O Sentieys - Microprocessors and …, 2014 - Elsevier
Minimizing the energy consumption and silicon area are usually two major challenges in the
design of battery-powered embedded computing systems. Dynamic and Partial …

Runtime task scheduling for FPGA-based embedded systems using just-in-time bitstream prefetching

A Duhamel, S Pillement - IEEE Access, 2024 - ieeexplore.ieee.org
Dynamically and partially reconfigurable Field Programmable Gate Arrays (FPGAs) offer
high performances and flexibility. These platforms can hot-swap reconfigurable regions to …

Improving the Energy Efficiency of CNN Inference on FPGA using Partial Reconfiguration

Z Li, S Bilavarn - International Workshop on Design and Architecture for …, 2024 - Springer
With the increasing demand for edge AI application scenarios, as the most popular deep
learning models, Convolutional Neural Networks (CNNs) need advanced solutions for the …

Dynamic reconfiguration of modular I/O IP cores for avionic applications

V Viswanathan, B Nakache, RB Atitallah… - 2012 International …, 2012 - ieeexplore.ieee.org
Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in
different application domains. However little has been explored in the avionic …

Performance enhancement of encryption and authentication IP cores for IPSec based on multiple-core architecture and dynamic partial reconfiguration on FPGA

TT Nguyen, VC Nguyen, TV Huynh… - … on Recent Advances …, 2018 - ieeexplore.ieee.org
In this paper, we propose a Multiple Core architecture and an DMA bus connectivity to
increase the processing speed of encryption and authentication cores in high speed IPSec …

Zynq‐Based Reconfigurable System for Real‐Time Edge Detection of Noisy Video Sequences

I Yoon, H Joung, J Lee - Journal of Sensors, 2016 - Wiley Online Library
We implement Zynq‐based self‐reconfigurable system to perform real‐time edge detection
of 1080p video sequences. While object edge detection is a fundamental tool in computer …