A multi-functional in-memory inference processor using a standard 6T SRAM array
A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS
process is presented. The prototype employs a deep in-memory architecture (DIMA), which …
process is presented. The prototype employs a deep in-memory architecture (DIMA), which …
Deep in-memory architectures in SRAM: An analog approach to approximate computing
M Kang, SK Gonugondla… - Proceedings of the …, 2020 - ieeexplore.ieee.org
This article provides an overview of recently proposed deep in-memory architectures
(DIMAs) in SRAM for energyand latency-efficient hardware realization of machine learning …
(DIMAs) in SRAM for energyand latency-efficient hardware realization of machine learning …
The Internet of Things on its edge: Trends toward its tipping point
M Alioto, M Shahghasemi - IEEE Consumer Electronics …, 2017 - ieeexplore.ieee.org
In this article, a review of commercial devices on the edge of the Internet of Things (IoT), or
IoT nodes, is presented in terms of hardware requirements. IoT nodes are the interface …
IoT nodes, is presented in terms of hardware requirements. IoT nodes are the interface …
Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node
Binary Neural Networks (BNNs) have been shown to be robust to random bit-level noise,
making aggressive voltage scaling attractive as a power-saving technique for both logic and …
making aggressive voltage scaling attractive as a power-saving technique for both logic and …
Circuit-level techniques for logic and memory blocks in approximate computing systemsx
This article presents an overview of circuit-level techniques used for approximate computing
(AC), including both computation and data storage units. After providing some background …
(AC), including both computation and data storage units. After providing some background …
Energy-quality scalable integrated circuits and systems: Continuing energy scaling in the twilight of Moore's law
This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable
circuits and systems, as promising direction to continue the historical exponential energy …
circuits and systems, as promising direction to continue the historical exponential energy …
E2CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices
To reduce energy consumption, it is possible to operate embedded systems at sub-nominal
conditions (eg, reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in …
conditions (eg, reduced voltage, limited eDRAM refresh rate) that can introduce bit errors in …
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing
M Alioto - Design, Automation & Test in Europe Conference & …, 2017 - ieeexplore.ieee.org
In this paper, the concept of energy-quality (EQ) scalable systems is introduced and
explored, as novel design dimension to scale down energy in integrated systems for the …
explored, as novel design dimension to scale down energy in integrated systems for the …
A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes
The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT)
based health monitoring system. The cell executes improved write and read ability using …
based health monitoring system. The cell executes improved write and read ability using …
Approximate SRAMs with dynamic energy-quality management
In this paper, approximate SRAMs are explored in the context of error-tolerant applications,
in which energy is saved at the cost of the occurrence of read/write errors (ie, signal quality …
in which energy is saved at the cost of the occurrence of read/write errors (ie, signal quality …