Enhanced segmented channel MOS transistor with multi layer regions
TJK Liu, Q Lu - US Patent 8,466,490, 2013 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
components formed in or on a common substrate including semiconductor components …
Gate line edge roughness model for estimation of FinFET performance variability
We present a model for estimating the impact of gate line edge roughness (LER) on the
performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG …
performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG …
Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
AB Sachid, R Francis, MS Baghini… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T FIN)
necessary to maintain acceptable short-channel performance. For the 45 nm technology …
necessary to maintain acceptable short-channel performance. For the 45 nm technology …
SRAM read/write margin enhancements using FinFETs
A Carlson, Z Guo, S Balasubramanian… - IEEE transactions on …, 2009 - ieeexplore.ieee.org
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the
scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to …
scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to …
Modeling and significance of fringe capacitance in nonclassical CMOS devices with gate–source/drain underlap
SH Kim, JG Fossum, JW Yang - IEEE transactions on electron …, 2006 - ieeexplore.ieee.org
Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS
devices, eg, double-gate (DG) MOSFETs, is shown, using two-dimensional numerical …
devices, eg, double-gate (DG) MOSFETs, is shown, using two-dimensional numerical …
Nanowire FET with corner spacer for high-performance, energy-efficient applications
Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total
device capacitance which degrades device and circuit performance. This problem is …
device capacitance which degrades device and circuit performance. This problem is …
Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap
X Sun, Q Lu, V Moroz, H Takeuchi… - IEEE Electron …, 2008 - ieeexplore.ieee.org
A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an
evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations …
evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations …
Effectiveness of stressors in aggressively scaled FinFETs
The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility
enhancement in aggressively scaled FinFETs are studied for different stressor technologies …
enhancement in aggressively scaled FinFETs are studied for different stressor technologies …
Design optimization of multigate bulk MOSFETs
The design optimization of multigate bulk MOSFET structures is investigated for sub-20-nm
gate lengths. Three-dimensional device simulations were used to optimize device design …
gate lengths. Three-dimensional device simulations were used to optimize device design …
An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects
This paper presents an analytical subthreshold model for surface potential and threshold
voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect …
voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect …