An iterative logarithmic multiplier

Z Babić, A Avramović, P Bulić - Microprocessors and Microsystems, 2011 - Elsevier
Digital signal processing algorithms often rely heavily on a large number of multiplications,
which is both time and power consuming. However, there are many practical solutions to …

Efficient hardware-based image compression schemes for wireless sensor networks: A survey

KK Hasan, UK Ngah, MFM Salleh - Wireless personal communications, 2014 - Springer
Multidimensional sensors, such as digital camera sensors in the visual sensor networks
VSNs generate a huge amount of information compared with the scalar sensors in the …

Applicability of approximate multipliers in hardware neural networks

U Lotrič, P Bulić - Neurocomputing, 2012 - Elsevier
In recent years there has been a growing interest in hardware neural networks, which
express many benefits over conventional software models, mainly in applications where …

Low power hardware-based image compression solution for wireless camera sensor networks

ML Kaddachi, A Soudani, V Lecuire, K Torki… - Computer Standards & …, 2012 - Elsevier
In this paper, we present and evaluate a hardware solution for user-driven and packet loss
tolerant image compression, especially designed to enable low power image compression …

An efficient distributed arithmetic based VLSI architecture for DCT

VK Sharma, KK Mahapatra… - … Conference on Devices …, 2011 - ieeexplore.ieee.org
Discrete cosine transform (DCT) is widely used in image and video compression standards.
This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low …

A simple pipelined logarithmic multiplier

P Bulić, Z Babić, A Avramović - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
Digital signal processing algorithms often rely heavily on a large number of multiplications,
which is both time and power consuming. However, there are many practical solutions to …

Design and performance analysis of a zonal DCT-based image encoder for Wireless Camera Sensor Networks

ML Kaddachi, A Soudani, V Lecuire, L Makkaoui… - Microelectronics …, 2012 - Elsevier
Systems mapped on CMOS architectures are often expected to achieve high processing
bandwidth and low energy consumption. However, a specific care should be paid to …

Exploring the Implementation of JPEG Compression on FPGA

AM De Silva, DG Bailey… - 2012 6th International …, 2012 - ieeexplore.ieee.org
This paper presents the implementation of the JPEG compression on a field programmable
gate array as the data are streamed from the camera. The goal was to minimise the logic …

Power and Area Optimization Techniques for Reconfigurable Inverse Discrete Cosine Transform FPGA for High Performance Computation Electromagnetics

R Radhika, S Dinesh, S Harini, S Kaviya… - … on Smart Structures …, 2023 - ieeexplore.ieee.org
Multimedia communications like image and video demand a significant amount of
bandwidth during data transmissionin uncompressed form. Despite advancements in …

RAM-ROM sebagai Pendukung Algoritma Zigzag Scan Menggunakan Metode Pemetaan pada Kompresi Citra Real-Time

R Candra - Jurnal Teknologi Informasi dan Ilmu Komputer, 2024 - jtiik.ub.ac.id
Konsep pengiriman informasi yang meliputi berbagai macam format data dengan proses
yang cepat (real-time) semakin dibutuhkan untuk berbagai kebutuhan, hal ini harus …