Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters
SA Zahrai, M Onabajo - Journal of Low Power Electronics and …, 2018 - mdpi.com
This article reviews design challenges for low-power CMOS high-speed analog-to-digital
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
A reconfigurable 10-to-12-b 80-to-20-MS/s bandwidth scalable SAR ADC
An asynchronous successive approximation register analog-to-digital converter (ADC) for
wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s …
wideband multi-standard systems is presented. The ADC can be configured as an 80-MS/s …
A 1-V 100-MS/s 8-bit CMOS switched-opamp pipelined ADC using loading-free architecture
PY Wu, VSL Cheung, HC Luong - IEEE Journal of Solid-State …, 2007 - ieeexplore.ieee.org
A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A
novel loading-free architecture is proposed to reduce the capacitive loading and to improve …
novel loading-free architecture is proposed to reduce the capacitive loading and to improve …
A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications
J Li, X Zeng, L Xie, J Chen, J Zhang… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter
(ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient …
(ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient …
A 9-bit 80 MS/s successive approximation register analog-to-digital converter with a capacitor reduction technique
A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which
is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of …
is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of …
Design of analog to digital converter using CMOS logic
The real world signals are all analog in nature. The digital signals and digital circuits offer
greater advantages as compared to analog circuits in processing speed and efficient …
greater advantages as compared to analog circuits in processing speed and efficient …
Privacy-preserving publication of mobility data with high utility
V Primault, SB Mokhtar, L Brunie - 2015 IEEE 35th …, 2015 - ieeexplore.ieee.org
An increasing amount of mobility data is being collected every day by different means, eg,
By mobile phone operators. This data is sometimes published after the application of simple …
By mobile phone operators. This data is sometimes published after the application of simple …
Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters
Settling behavior of operational amplifiers is of great importance in many applications. In this
paper, an efficient methodology for the design of high-speed two-stage operational …
paper, an efficient methodology for the design of high-speed two-stage operational …
[图书][B] Modeling, identification, and compensation of channel mismatch errors in time-interleaved analog-to-digital converters
C Vogel - 2005 - academia.edu
Modern signal processing applications emerging in telecommunication and instrumentation
industries need high-speed analog-to-digital converters (ADCs), which can be achieved by …
industries need high-speed analog-to-digital converters (ADCs), which can be achieved by …
Design and implementation of CMOS rail-to-rail operational amplifiers
MAG Lorenzo, AAS Manzano… - 2007 International …, 2007 - ieeexplore.ieee.org
The paper presents the design and implementation of six operational amplifiers with rail-to-
rail input and output capability. The study characterizes several rail-to-rail input and output …
rail input and output capability. The study characterizes several rail-to-rail input and output …