A novel heuristic search method for two-level approximate logic synthesis

S Su, C Zou, W Kong, J Han… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Recently, much attention has been paid to approximate computing, a novel design paradigm
for error-tolerant applications. It can significantly reduce area, power, and delay of circuits by …

Approximate logic synthesis by genetic algorithm with an error rate guarantee

CT Lee, YT Li, YC Chen, CY Wang - Proceedings of the 28th Asia and …, 2023 - dl.acm.org
Approximate computing is an emerging design technique for error-tolerant applications,
which may improve circuit area, delay, or power consumption by trading off a circuit's …

Area-driven Boolean bi-decomposition by function approximation

A Bernasconi, V Ciriani, J Cortadella, M Costa… - ACM Transactions on …, 2024 - dl.acm.org
Bi-decomposition rewrites logic functions as the composition of simpler components. It is
related to Boolean division, where a given function is rewritten as the product of a divisor …

An efficient approximate node merging with an error rate guarantee

KS Tam, CC Lin, YC Chen, CY Wang - Proceedings of the 26th Asia and …, 2021 - dl.acm.org
Approximate computing is an emerging design paradigm for error-tolerant applications. eg,
signal processing and machine learning. In approximate computing, the area, delay, or …

Threshold function identification by redundancy removal and comprehensive weight assignments

CH Liu, CC Lin, YC Chen, CC Wu… - … on Computer-Aided …, 2018 - ieeexplore.ieee.org
The identification of threshold function (TF), which determines whether a Boolean function
can be represented by an linear threshold logic gate (LTG) or not, is a fundamental but …

9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function

YC Yen, MJ Li, YT Li, YC Chen, I Chen… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Identification of a Threshold Function (TF) is a significant task that determines whether a
given Boolean function is a TF or not. The state-of-the-art only identifies all 8-input NP-class …

Exploiting symmetrization and D-reducibility for approximate logic synthesis

A Bernasconi, V Ciriani, T Villa - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Approximate synthesis is a recent trend in logic synthesis where one changes some outputs
of a logic specification, within the error tolerance of a given application, to reduce the …

Approximate logic synthesis by symmetrization

A Bernasconi, V Ciriani, T Villa - … & Test in Europe Conference & …, 2019 - ieeexplore.ieee.org
Approximate synthesis is a recent trend in logic synthesis that changes some outputs of a
logic specification to take advantage of error tolerance of some applications and reduce …

An Efficient Approach to Iterative Network Pruning

CS Huang, W Tang, YC Chen, YT Li… - … VLSI Symposium on …, 2024 - ieeexplore.ieee.org
Network pruning is a technique to minimize the number of parameters of large neural
networks. Network pruning can be performed once or multiple times. One-shot network …

Multiply-accumulate enhanced BDD-based logic synthesis on RRAM crossbars

S Froehlich, S Shirinzadeh… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
Resistive random access memory (RRAM) is a nonvolatile memory technology which allows
to perform computations in both digital and analog circuits. Multiply-Accumulate (MAC) is an …