KS Stevens - US Patent App. 13/945,843, 2014 - Google Patents
Technology for generating a relative timing architecture using a relative timed module is disclosed. In an example, an electronic design automation (EDA) tool enabled for clocked …
R Segal, P Zou - US Patent 8,914,759, 2014 - Google Patents
Abstract Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths …
R Segal, P Zou - US Patent 9,390,222, 2016 - Google Patents
Some embodiments described herein provide methods and systems for creating a circuitabstraction that can significantly improve performance of floorplanning and circuit …