Single Miller capacitor frequency compensation techniques: Theoretical comparison and critical review

AD Grasso, D Marano, G Palumbo… - International Journal of …, 2022 - Wiley Online Library
This paper presents a systematic analytical comparison of the single‐Miller capacitor
frequency compensation techniques suitable for three‐stage complementary metal–oxide …

Design of three-stage OTA based on settling-time requirements including large and small signal behavior

G Giustolisi, G Palumbo - … on Circuits and Systems I: Regular …, 2020 - ieeexplore.ieee.org
In this paper we are going to analyze the settling-time in single-, two-and three-stage
amplifiers with the intent of deriving approximate but useful design equations that include …

The design of fast-settling three-stage amplifiers using the open-loop damping factor as a design parameter

R Nguyen, B Murmann - … Transactions on Circuits and Systems I …, 2010 - ieeexplore.ieee.org
This paper presents an open-loop design method for fast-settling three-stage class-A
amplifiers. Specifically, using the open-loop damping factor as a design parameter, the …

Design of CMOS three-stage amplifiers for near-to-minimum settling-time

G Giustolisi, G Palumbo - Microelectronics Journal, 2021 - Elsevier
In this paper, we provide a new procedure that allows to design a generic three-stage
amplifier from settling-time specifications. The procedure analyze the settling-time of pure …

In-depth analysis of pole-zero compensations in CMOS operational transconductance amplifiers

G Giustolisi, G Palumbo - … on Circuits and Systems I: Regular …, 2019 - ieeexplore.ieee.org
In this paper we explore the effects of pole-zero compensation in the settling performance of
operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a …

Settling time optimization for three-stage CMOS amplifier topologies

A Pugliese, FA Amoroso, G Cappuccino… - … on Circuits and …, 2009 - ieeexplore.ieee.org
A new settling-time-oriented design methodology for the most common three-stage
operational amplifier (op-amp) schemes reported in the literature is presented in this paper …

[PDF][PDF] Design of a high frequency low voltage CMOS operational amplifier

P Kakoty - International Journal of VLSI design & communication …, 2011 - Citeseer
ABSTRACT A method is presented in this paper for the design of a high frequency CMOS
operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron …

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

G Giustolisi, G Palumbo - Journal of Low Power Electronics and …, 2021 - mdpi.com
In this paper, a new strategy for the design of ultra-low-power CMOS operational
transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet …

Three-stage dynamic-biased CMOS amplifier with a robust optimization of the settling time

G Giustolisi, G Palumbo - … on Circuits and Systems I: Regular …, 2015 - ieeexplore.ieee.org
In this paper a three-stage dynamic-biased CMOS amplifier is designed with a robust
optimization of its settling-time performance. The methodology studies the stability of a third …

A new class of continuous-time delay-compensated parameter-varying low-pass elliptic filters with improved dynamic behavior

J Piskorowski, MÁG De Anda - IEEE Transactions on Circuits …, 2008 - ieeexplore.ieee.org
In some applications, it is required to have continuous-time low-pass analog filtering
systems which simultaneously possess a constant group delay in the passband and a …