Arithmetic logic unit using diode free adiabatic logic and selection unit for adiabatic logic family

V Grover, V Gosain, N Pandey… - 2018 5th International …, 2018 - ieeexplore.ieee.org
Reduction in energy dissipation is an active area of research. Systems which consume
power require the deployment of expensive cooling systems. In this paper a 1-bit ALU circuit …

An application of the RMMAC methodology to an unstable plant

V Hassani, M Athans… - 2009 17th Mediterranean …, 2009 - ieeexplore.ieee.org
In this paper we extend and generalize previous work on robust adaptive control of
uncertain plants using multiple models (the RMMAC methodology). We formulate and study …

Design of Low Power ECRL Based Power Gated 4: 2 Compressor

N Malhotra, A Mann, N Pandey - 2019 6th International …, 2019 - ieeexplore.ieee.org
Advent of new age technologies like augmented reality (AR) has made techniques like
digital signal processing (DSP), image and speech processing one of the most frequently …

Pre-scalar for Diode Free Adiabatic Logic family

N Pandey, K Gupta, T Kuhar - 2016 International Conference …, 2016 - ieeexplore.ieee.org
The appetency for high performance electronic devices in today's time imposes constraints
on designers to make low power circuits. Various circuit styles and techniques are adopted …

Implementation of 4-BIT universal shift register using diode free adiabatic logic

S Pervez, M Sahoo, A Noor - 2017 8th International …, 2017 - ieeexplore.ieee.org
In digital circuits, shift registers are used as the basic memory units. This paper presents a
low power adiabatic Universal Shift Register, which can perform both serial and parallel shift …

Power Gated ECRL Adiabatic Logic Based Optimized Two-Input Multiplexer

A Mann, N Malhotra, A Wadhwa… - 2020 IEEE 17th India …, 2020 - ieeexplore.ieee.org
In this paper, the effect of header and footer power gating techniques is examined in the
context of Efficient Charge Recovery Logic (ECRL) based two input multiplexer (MUX) …

Design and Analysis of Ultra-Low Power Adiabatic Computational Subsystem Based on Symmetric Stacking

P Ravali, P Panda, M Rao - … on VLSI Design and Test (VDAT), 2020 - ieeexplore.ieee.org
A novel design is proposed for the implementation of low power efficient charge recovery
logic (ECRL) based adiabatic driven computational subsystem. An ultra-low power adiabatic …

AN ENERGY-EFFICIENT ADIABATIC LOGIC BASED LFSR.

MK Saini, N Pandey - I-Manager's Journal on Circuits & …, 2019 - search.ebscohost.com
Today's major challenge in designing electronic circuits is to deliver high-performance with
minimal power dissipation. While electronic devices have achieved tremendous …

DFAL BASED FLEXIBLE MULTI-MODULO PRESCALER

N Pandey, K Gupta, MK Saini - ICTACT …, 2016 - repository.journal4submission.com
The quest to have longer battery life and reduced packaging cost has been motivating factor
behind developing low power circuits for different applications. Research in adiabatic logic …

[引用][C] COMPARATIVE ANALYSIS OF ALU DESIGN USING DFAL AND TRANSMISSION GATES

S JAYAVARDHAN