Power reduction using high speed with saving mode clock gating technique

M Hameed, HS Mogheer… - IOP Conference Series …, 2021 - iopscience.iop.org
The demand for low power consumption is motivated by several factors such as the
evolution of portable design, reliability effects, and flexibility. The purpose of clock gating is …

Dynamic Power Reduction in Huffman Design using 130 nm Technology Library

M Hameed, AL Hameed… - … Conference on Computer …, 2022 - ieeexplore.ieee.org
The demand for data compression and decreased dissipated power is motivated by many
features, like following a new model for portable design, reliability effects, and flexibility. The …

Low power approach for implementation of 8B/10B encoder and 10B/8B decoder used for high speed communication

K Sahni, K Rawat, S Pandey… - 2014 2nd International …, 2014 - ieeexplore.ieee.org
In this paper a clock gated 8B/10B encoder and 10B/8B decoder circuit is implemented. In
this we design the encoder decoder circuit with gated clock as it optimized the power without …

Evaluation of 8b/10b FPGA encoder implementations for SerDes links

A Quesada-Martínez, J Aparicio-Morales… - 2020 IEEE 11th Latin …, 2020 - ieeexplore.ieee.org
In this work, alternatives to implement 8b/10b encoders in FPGAs for serializer-deserializer
links are evaluated. Custom implementations based on decoders and look-up tables are …

Power optimization of communication system using clock gating technique

K Sahni, K Rawat, S Pandey… - 2015 Fifth International …, 2015 - ieeexplore.ieee.org
A power optimized communication system is proposed in this paper with clock gating
technique. The encoder decoder block and the converter circuits are designed using clock …

Verification of SerDes Design Using UVM Methodology

KA Nagesh, DR Shilpa - Proceeding of Fifth International Conference on …, 2021 - Springer
There has always been a need to transmit data since the computer's inception. When data is
sent out of the network, it will require cable sizes to carry the data. To ease the data …

Optimization of Physical Layer Modules of USB 3.0 Using FPGA

P Bhulania, Y Chitransh, K Sharma… - 2020 4th International …, 2020 - ieeexplore.ieee.org
Super speed bus communication is achieved through USB 3.0 architecture due to its dual-
bus architecture. The main purpose of this research work is to reduce the power …

[PDF][PDF] Design of the Readout Chip with Multi-Energy Bins for Spectroscopic X-ray Imaging

J Cai - 2024 - tesidottorato.depositolegale.it
Spectroscopic X-ray imaging is an important development direction in the field of medical CT
in recent years. Spectroscopic CT can detect X-rays in multiple energy ranges …

Design and verification of 8b/10b encoder/decoder for USB 3.0 applications

K Sahni, K Rawat, S Pandeyl, J Rawat… - … and Control (IC4), 2015 - ieeexplore.ieee.org
In this paper we have implemented the 8× 10 encoder and 10× 8 decoder with 3-bit down
ripple counter. Ripple counter is one of the techniques for reducing the clock skew problem …

One solution of complex ADAS HW system testing

B Kragulj, S Laza, M Milosevic… - 2017 25th …, 2017 - ieeexplore.ieee.org
The trend of installing Advanced Driver Assistance Systems (ADAS) in vehicles is entering
from the “desired” to “mandatory requirement” phase. In addition, the number of features …