A survey on fault-tolerant application mapping techniques for network-on-chip
N Kadri, M Koudil - Journal of Systems Architecture, 2019 - Elsevier
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …
techniques have been proposed in the literature to deal with different types of faults at …
SPANNER: A self-repairing spiking neural network hardware architecture
Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism
in the human brain, where spiking neurons provide direct and indirect feedbacks to …
in the human brain, where spiking neurons provide direct and indirect feedbacks to …
Pars network: a multistage interconnection network with fault-tolerance capability
F Bistouni, M Jahanshahi - Journal of Parallel and Distributed Computing, 2015 - Elsevier
Interconnection networks are used for communication between nodes in multi-processor
systems as well as super-systems. These systems require effective communication between …
systems as well as super-systems. These systems require effective communication between …
Exploring self-repair in a coupled spiking astrocyte neural network
It is now known that astrocytes modulate the activity at the tripartite synapses where indirect
signaling via the retrograde messengers, endocannabinoids, leads to a localized self …
signaling via the retrograde messengers, endocannabinoids, leads to a localized self …
Scalable networks-on-chip interconnected architecture for astrocyte-neuron networks
Spiking astrocyte-neuron networks (ANNs) have the potential to emulate the self-repair
capability in the mammalian brain. Recent research has explored the mimicking of this …
capability in the mammalian brain. Recent research has explored the mimicking of this …
Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead
Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC)
due to the increase in physical defects in advanced manufacturing processes. Two novel …
due to the increase in physical defects in advanced manufacturing processes. Two novel …
Low cost fault-tolerant routing algorithm for networks-on-chip
A novel adaptive routing algorithm–Efficient Dynamic Adaptive Routing (EDAR) is proposed
to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path …
to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path …
Efficient design-for-test approach for networks-on-chip
To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
On error injection for NoC platforms: a UVM-based generic verification environment
S El-Ashry, M Khamis, H Ibrahim… - … on Computer-Aided …, 2019 - ieeexplore.ieee.org
Error injection has become critically important for testing the reliability of newly designed
hardware systems. Evaluating how a design under test (DUT) reacts to different error …
hardware systems. Evaluating how a design under test (DUT) reacts to different error …
Bio-inspired fault detection circuits based on synapse and spiking neuron models
Recent studies have shown that the electronic hardware devices can be compromised by
the faults and fault tolerance is a crucial capability. This paper addresses the challenge of …
the faults and fault tolerance is a crucial capability. This paper addresses the challenge of …