Silent data corruptions at scale

HD Dixit, S Pendharkar, M Beadon, C Mason… - arXiv preprint arXiv …, 2021 - arxiv.org
Silent Data Corruption (SDC) can have negative impact on large-scale infrastructure
services. SDCs are not captured by error reporting mechanisms within a Central Processing …

Identifying resistive open defects in embedded cells under variations

ZP Najafi-Haghi, HJ Wunderlich - Journal of Electronic Testing, 2023 - Springer
Abstract Small Delay Faults (SDFs) due to weak defects and marginalities have to be
distinguished from extra delays due to process variations, since they may form a reliability …

Resistive open defect classification of embedded cells under variations

ZP Najafi-Haghi, HJ Wunderlich - 2021 IEEE 22nd Latin …, 2021 - ieeexplore.ieee.org
Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from
extra delays due to process variations, since they may form a reliability threat even if the …

BiSTAHL: A built-in self-testable soft-error-hardened scan-cell

S Holst, R Ma, X Wen, A Yan… - 2023 IEEE European Test …, 2023 - ieeexplore.ieee.org
Ensuring the correct operation of modern VLSI circuits within safety-critical systems is
essential since modern technology nodes are more susceptible to Early-Life Failures (ELFs) …

Variation-aware defect characterization at cell level

ZP Najafi-Haghi, M Hashemipour-Nazari… - 2020 IEEE European …, 2020 - ieeexplore.ieee.org
Small Delay Faults (SDFs) are an indicator of reliability threats even if they do not affect the
behavior of a system at nominal speed. Various defects may evolve over time into a …

On extracting reliability information from speed binning

ZP Najafi-Haghi, F Klemme, H Amrouch… - 2022 IEEE European …, 2022 - ieeexplore.ieee.org
Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-
induced variability challenges for advanced high-performance circuits. AVFS requires and …

DEFCON: Defect Acceleration through Content Optimization

S Natarajan, A Sathaye, C Oak… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
During manufacturing of integrated circuits, it is imperative for cost and quality that defects
that occur on die are screened early in the test process, preferably before packaging. As part …

Stress-Aware Periodic Test of Interconnects

S Sadeghi-Kohan, S Hellebrand… - Journal of Electronic …, 2021 - Springer
Safety-critical systems have to follow extremely high dependability requirements as
specified in the standards for automotive, air, and space applications. The required high fault …

Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection

ZP Najafi-Haghi, F Klemme… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
Resistive open defects in FinFET circuits are reliability threats and should be ruled out
before deployment. The performance variations due to these defects are similar to the effect …

Using programmable delay monitors for wear-out and early life failure prediction

C Liu, E Schneider… - 2020 Design, Automation & …, 2020 - ieeexplore.ieee.org
Early life failures in marginal devices are a severe reliability threat in current nano-scaled
CMOS devices. While small delay faults are an effective indicator of marginalities, their …