Picowatt Dual-Output Voltage Reference Based on Leakage Current Compensation and Diode-Connected Voltage Divider

Y Huang, Y Luo, Y Zeng - Electronics, 2024 - search.proquest.com
A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this
paper based on a standard 65 nm process. To compensate for the leakage current caused …

A 180 nm self-biased bandgap reference with high PSRR enhancement

Y Shi, S Li, J Cao, Z Zhou, W Ling - Nanoscale Research Letters, 2020 - Springer
In this paper, an improved self-biased bandgap reference (BGR) with high power supply
rejection ratio (PSRR) is presented. An operational amplifier constructing feedback loop is …

[HTML][HTML] Proposed wide dynamic-range controllable current sources

SM Sharroush, YS Abdalla - Ain Shams Engineering Journal, 2023 - Elsevier
Generating ultra-low currents using resistors is impractical especially in integrated circuits
due to the wasting of much area associated with the required very large resistors. In this …

A 3.9 ppm/○ C, 31.5 ppm/V ultra-low-power subthreshold CMOS-only voltage reference

J Liao, Y Zeng, J Li, J Yang, HZ Tan - Microelectronics Journal, 2020 - Elsevier
This paper presents an ultra-low-power CMOS voltage reference based on the 0.18 μ m
standard CMOS technology. A temperature coefficient (TC) of 3.9 ppm/○ C without resistors …

TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

P Verma, AK Sharma, VS Pandey, A Noor - Analog Integrated Circuits and …, 2022 - Springer
Stupendous and inevitable applications of dynamic CMOS circuits add thrust to its
optimization to high-end performance. Dynamic logic circuits are very efficient in terms of …

A Comprehensive Study of Different Techniques for Voltage References

K Duggal, R Pandey, V Niranjan - Journal of Circuits, Systems and …, 2023 - World Scientific
In the analog and mixed-signal integrated circuits, voltage references that are independent
of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms …

A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

K Yu, J Zhang, S Li - IEICE Electronics Express, 2024 - jstage.jst.go.jp
This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-
power application. In the current generation path, a source degeneration active load (SDAL) …

16.8/15.2 ppm/° C 81 nW high PSRR dual-output voltage reference for portable biomedical application

H Yue, X Sun, J Liu, W Xu, H Li, B Wei, T Wang, S Lin - Electronics, 2019 - mdpi.com
A dual-output voltage reference circuit with two reference voltages of 281 mV (Vref1) and
320.5 mV (Vref2) is presented in this paper. With a novel and precise circuit structure, the …

Ultra‐low line sensitivity and high PSRR sub‐threshold CMOS voltage reference

M Rashtian - The Journal of Engineering, 2023 - Wiley Online Library
This paper presents a nanowatt CMOS voltage reference (VR) with ultra‐low line sensitivity
(LS) and high‐power supply ripple rejection (PSRR). The proposed VR consists of two …

0.55–1.8 V, 7.5 nW, 225.5 mV, CMOS‐only subthreshold voltage reference

Q Duan, X Wang, S Huang, Y Ding, Z Meng… - Electronics …, 2019 - Wiley Online Library
This Letter presents a wide supply voltage range, ultra‐low power, and CMOS‐only
subthreshold voltage reference. A complementary‐to‐absolute‐temperature () generator …