Methods for executing load instructions are disclosed. In one method, a load instruction and
corresponding thread information are received. Address information of the load instruction is …

The present disclosure is directed to novel methods and apparatus for managing or
performing the dynamic allocation or reallocation of processing resources among a vertex …

The present invention is directed to a user-level thread scheduler that employs a service that
propagates at the user level, continuously as it gets updated in the kernel, the kernel-level …

BACKGROUND 0001 Moore's Law says that the number of transistors we can fit on a silicon
wafer doubles every year or so. No exponential lasts forever, but we can reasonably expect …

The present invention addresses the shortcomings of existing SMT processors and CMPs by
integrating dedi cated thread-management into a CMP having processing units, interface …

Graphics processing units (GPUs) are used, for example, to process data related to three-
dimensional objects or scenes and to render the three-dimensional data onto a two …

A cache memory and method of operating a cache memory are provided. The cache
memory comprises cache storage that stores cache lines for a plurality of requesters and …

An apparatus for performing data processing in a single program multiple data fashion on a
target data set is provided, having execution circuitry configured to execute multiple threads …

A multithreading processor 4 interleaves program instructions from different program threads
to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors …

Methods and arrangements are provided for use in multiple user computing environments.
These methods and arrangements can be configured to allow for a plurality of separate and …