Bottleneck Crosstalk Minimisation in Two-and Three-Layer Manhattan Channel Routing

TN Mandal, S Sarkar, D Roy, A Khan, R Mehera… - IEEE …, 2024 - ieeexplore.ieee.org
VLSI physical design is a domain of work as old as more than five decades. Even then, as
technology progresses, there are several challenging issues from the perspective of …

On predictable reconfigurable system design

N Voss, B Kwaadgras, O Mencer, W Luk… - ACM Transactions on …, 2021 - dl.acm.org
We propose a design methodology to facilitate rigorous development of complex
applications targeting reconfigurable hardware. Our methodology relies on analytical …

Training a fully convolutional neural network to route integrated circuits

SR Jain, K Okabe - arXiv preprint arXiv:1706.08948, 2017 - arxiv.org
We present a deep, fully convolutional neural network that learns to route a circuit layout net
with appropriate choice of metal tracks and wire class combinations. Inputs to the network …

Algorithms for minimizing bottleneck crosstalk in two-layer channel routing

TN Mandal, AD Banik, K Dey, R Mehera… - … in Communication Circuits …, 2020 - Springer
Channel routing and crosstalk minimization are important issues while we talk about high-
performance circuits for VLSI physical design automation. Interconnection among the net …

[PDF][PDF] Algorithms for reducing crosstalk in two-layer channel routing

A Pal, D Kundu, AK Datta, TN Mandal… - Journal of Physical …, 2006 - academia.edu
Crosstalk minimization is one of the most important high performance aspects in
interconnecting VLSI circuits. With advancement of fabrication technology, devices and …

Crosstalk-aware global routing in VLSI design by using a shuffled frog-leaping algorithm

A Terapasirdsin, S Kiattisin - Journal of Mobile …, 2020 - journals.riverpublishers.com
Nowadays, very large scale integrated (VLSI) circuit technology is developing rapidly. It is
necessary to consider many factors related to the VLSI circuit design. Interference is one of …

[PDF][PDF] Application of graphs in computing reduced area VLSI channel routing solutions

A Pal, AK Khan, SS Sau, AK Datta, RK Pal… - Proc. of International …, 2010 - researchgate.net
Channel routing problem is a problem in VLSI physical design whose objective is to
compute a feasible minimum area routing solution. A channel is a rectangular routing region …

A graph theoretic approach to minimize total wire length in channel routing

P Mitra, N Ghoshal, RK Pal - TENCON 2003. Conference on …, 2003 - ieeexplore.ieee.org
Minimization of total (vertical) wire length in VLSI physical design automation is one of the
most important topics of current research. As fabrication technology advances, devices and …

Manhattan-diagonal routing in channels and switchboxes

S Das, S Sur-Kolay, BB Bhattacharya - ACM Transactions on Design …, 2004 - dl.acm.org
New techniques are presented for routing straight channels, L-channels, switchboxes, and
staircase channels in a two-layer Manhattan-diagonal (MD) model with tracks in horizontal …

A graph based algorithm to minimize total wire length in VLSI channel routing

SS Sau, A Pal, TN Mandal, AK Datta… - 2011 IEEE …, 2011 - ieeexplore.ieee.org
Minimization of total (vertical) wire length is one of the most important problems in laying out
blocks in VLSI physical design. Minimization of wire length not only reduces the cost of …