A review of self-heating effects in advanced CMOS technologies
C Prasad - IEEE Transactions on Electron Devices, 2019 - ieeexplore.ieee.org
The march toward dimensional scaling and higher performance has led the semiconductor
industry to consider nonplanar topologies and different material systems. These choices …
industry to consider nonplanar topologies and different material systems. These choices …
Self-heating in advanced CMOS technologies
On advanced technology nodes, increases in power density, non-planar architectures and
different material systems can exacerbate local self-heating due to active power dissipation …
different material systems can exacerbate local self-heating due to active power dissipation …
SCARe: an SRAM-based countermeasure against IC recycling
With the rapid growth of the electronics market, counterfeiting of integrated circuits (ICs), in
particular IC recycling, has become a serious issue in recent years. Recycled ICs are those …
particular IC recycling, has become a serious issue in recent years. Recycled ICs are those …
Comprehensive device and product level reliability studies on advanced CMOS technologies featuring 7nm high-k metal gate FinFET transistors
DS Huang, JH Lee, YS Tsai, YF Wang… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
In this study, a reliability study from device, circuit aging, and product reliability
characterization is systematically presented for the state-of-the-art 7nm FinFETs. The Bias …
characterization is systematically presented for the state-of-the-art 7nm FinFETs. The Bias …
Aging model challenges in deeply scaled tri-gate technologies
As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging
mechanisms become important to include in models to accurately predict end-of-life …
mechanisms become important to include in models to accurately predict end-of-life …
Aging measurement and empirical modeling of BTI on FPGA using 16 nm FinFETs for static and dynamic stresses
J Sobas, F Marc - Microelectronics Reliability, 2023 - Elsevier
This article presents an empirical modeling of BTI on 16 nm FinFET technology. This model
is based on a 5000 h aging test and measurements on Zynq UltraScale+ FPGAs with nine …
is based on a 5000 h aging test and measurements on Zynq UltraScale+ FPGAs with nine …
Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability
S Mukhopadhyay, YH Lee, JH Lee - Microelectronics Reliability, 2018 - Elsevier
In this study a careful analysis of the device and the circuit level variability and reliability are
presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET …
presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET …
A Fast Measurement (FVM) Technique for NBTI Behavior Characterization
In this letter, a novel fast threshold voltage (V th) measurement (FVM) technique is proposed
and demonstrated, which could perform IV characterization of MOSFETs within 1 ns. With …
and demonstrated, which could perform IV characterization of MOSFETs within 1 ns. With …
The impact and implication of BTI/HCI decoupling on ring oscillator
MH Hsieh, YC Huang, TY Yew… - 2015 IEEE …, 2015 - ieeexplore.ieee.org
In this study, a novel RO test structure is proposed and demonstrated to decouple the impact
of BTI and HCI effect in RO degradation. The frequency dependence of RO degradation is …
of BTI and HCI effect in RO degradation. The frequency dependence of RO degradation is …
Pentimento: Data remanence in cloud FPGAs
Remote attackers can recover" FPGA pentimento"-long-removed data belonging to a prior
user or proprietary design image on a cloud FPGA. Just as a pentimento of a painting can be …
user or proprietary design image on a cloud FPGA. Just as a pentimento of a painting can be …