Technology prospects for data-intensive computing
K Akarvardar, HSP Wong - Proceedings of the IEEE, 2023 - ieeexplore.ieee.org
For many decades, progress in computing hardware has been closely associated with
CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency …
CMOS logic density, performance, and cost. As such, slowdown in 2-D scaling, frequency …
Conflict-aware compiler for hierarchical register file on GPUs
Modern graphics processing units (GPUs) leverage a high degree of thread-level
parallelism, necessitating large-sized register files for storing numerous thread contexts. To …
parallelism, necessitating large-sized register files for storing numerous thread contexts. To …
TEA-RC: Thread Context-Aware Register Cache for GPUs
Graphics processing units (GPUs) achieve high throughput by exploiting a high degree of
thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register …
thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register …
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization
Recent GPUs provisioned with large register files (RFs) cannot fully utilize the bandwidth
between the RFs and execution pipelines, as the current policy for allocating operand (OP) …
between the RFs and execution pipelines, as the current policy for allocating operand (OP) …