A survey of architectural approaches for data compression in cache and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …

Base-delta-immediate compression: Practical data compression for on-chip caches

G Pekhimenko, V Seshadri, O Mutlu… - Proceedings of the 21st …, 2012 - dl.acm.org
Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

S Kargar, F Nawab - Distributed and Parallel Databases, 2023 - Springer
Recently, non-volatile memory (NVM) technology has revolutionized the landscape of
memory systems. With many advantages, such as non volatility and near zero standby …

A large-scale empirical study on self-admitted technical debt

G Bavota, B Russo - Proceedings of the 13th international conference …, 2016 - dl.acm.org
Technical debt is a metaphor introduced by Cunningham to indicate" not quite right code
which we postpone making it right". Examples of technical debt are code smells and bug …

Adaptive cache compression for high-performance processors

AR Alameldeen, DA Wood - ACM SIGARCH Computer Architecture …, 2004 - dl.acm.org
Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …

Scaling the bandwidth wall: challenges in and avenues for CMP scaling

BM Rogers, A Krishna, GB Bell, K Vu, X Jiang… - Proceedings of the 36th …, 2009 - dl.acm.org
As transistor density continues to grow at an exponential rate in accordance to Moore's law,
the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-chip …

Linearly compressed pages: A low-complexity, low-latency main memory compression framework

G Pekhimenko, V Seshadri, Y Kim, H Xin… - Proceedings of the 46th …, 2013 - dl.acm.org
Data compression is a promising approach for meeting the increasing memory capacity
demands expected in future systems. Unfortunately, existing compression algorithms do not …

C-pack: A high-performance microprocessor cache compression algorithm

X Chen, L Yang, RP Dick, L Shang… - IEEE transactions on …, 2009 - ieeexplore.ieee.org
Microprocessor designers have been torn between tight constraints on the amount of on-
chip cache memory and the high latency of off-chip memory, such as dynamic random …

A robust main-memory compression scheme

M Ekman, P Stenstrom - 32nd International Symposium on …, 2005 - ieeexplore.ieee.org
Lossless data compression techniques can potentially free up more than 50% of the memory
resources. However, previously proposed schemes suffer from high access costs. The …

MIRA: A multi-layered on-chip interconnect router architecture

D Park, S Eachempati, R Das, AK Mishra… - ACM SIGARCH …, 2008 - dl.acm.org
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the
interconnect delay problem for designing CMP/multi-core/SoC systems in deep sub-micron …