Materials, processing and reliability of low temperature bonding in 3D chip stacking
Due to the advantages of small form factor, high performance, low power consumption, and
high density integration, three-dimensional integrated circuits (3D ICs) have been generally …
high density integration, three-dimensional integrated circuits (3D ICs) have been generally …
Silicon photonics for extreme scale systems
High-performance systems are increasingly bottlenecked by the growing energy and
communications costs of interconnecting numerous compute and memory resources …
communications costs of interconnecting numerous compute and memory resources …
Heterogeneous 2.5 D integration on through silicon interposer
Driven by the need to reduce the power consumption of mobile devices, and servers/data
centers, and yet continue to deliver improved performance and experience by the end …
centers, and yet continue to deliver improved performance and experience by the end …
Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration
JH Lau - … symposium on advanced packaging materials (APM), 2011 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
Overview and outlook of three-dimensional integrated circuit packaging, three-dimensional Si integration, and three-dimensional integrated circuit integration
JH Lau - Journal of Electronic Packaging, 2014 - asmedigitalcollection.asme.org
3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC
integration. They are different and in general the through-silicon via (TSV) separates 3D IC …
integration. They are different and in general the through-silicon via (TSV) separates 3D IC …
Wafer-level vacuum packaging of smart sensors
A Hilton, DS Temple - Sensors, 2016 - mdpi.com
The reach and impact of the Internet of Things will depend on the availability of low-cost,
smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and …
smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and …
3D Integration
JH Lau, JH Lau - Fan-Out Wafer-Level Packaging, 2018 - Springer
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Find a journal Publish with us Track your research Search Cart Book cover Fan-Out …
Find a journal Publish with us Track your research Search Cart Book cover Fan-Out …
Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration
CK Lee, TC Chang, YJ Huang, HC Fu… - 2011 IEEE 61st …, 2011 - ieeexplore.ieee.org
In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are
designed and fabricated. The chip size is 5mm× 5mm with thousands of microbumps. A …
designed and fabricated. The chip size is 5mm× 5mm with thousands of microbumps. A …
High-density large-area-array interconnects formed by low-temperature Cu/Sn–Cu bonding for three-dimensional integrated circuits
MR Lueck, JD Reed, CW Gregory… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
High-density area-array 3-D interconnects are a key enabling technology for 3-D integrated
circuits. This paper presents results of the fabrication and testing of large 640 by 512 area …
circuits. This paper presents results of the fabrication and testing of large 640 by 512 area …
Wafer bumping, assembly, and reliability of fine-pitch lead-free micro solder joints for 3-D IC integration
CK Lee, TC Chang, JH Lau, YJ Huang… - IEEE Transactions …, 2012 - ieeexplore.ieee.org
In this investigation, Cu-Sn lead-free solder microbumps on 10-μ\rmm pads with a 20-μ\rmm
pitch are designed and fabricated. The chip size is 5 \,*\, 5 mm with thousands of …
pitch are designed and fabricated. The chip size is 5 \,*\, 5 mm with thousands of …