Recent advances in semiconductor technology offer vertical interconnect access (via) that
extend through silicon, popularly known as through silicon via (TSV). This book provides a …

Purpose–The purpose of this paper is to explore the functioning of very‐large‐scale
integration (VLSI) interconnects and modeling of interconnects and evaluate different …

Abstmct-Interconnect between a CMOS driver and receiver can be modeled as a lossy
transmission line in high speed CMOS VLSI circuits as transition times become comparable …

As the operating frequency increases to gigahertz and the rise time of a signal is less than or
comparable to the time-of-flight delay of a wire, it is necessary to consider the transmission …

On-chip parasitic inductance has become an important design issue in high speed
integrated circuits. On-chip inductance may degrade on-chip signal quality, affect …

A Fourier analysis of on-chip signals in CMOS integrated circuits is presented in this paper. It
is demonstrated that on-chip signals can be approximated by a Fourier series up to the 15th …

Interconnects have received attention as a source of crosstalk to other interconnects, but
have been ignored as a source of substrate noise. The importance of interconnect-induced …

Interconnect in VLSI circuits is best modeled as a lossy transmission line in high speed
integrated circuits. Analytical expressions for the coupling noise between adjacent …

Inductance modeling for on-chip interconnects in a typical digital environment is proposed.
Regarding the effective loop inductance computation, the issue of current return path …

As the operating frequency increases to giga hertz and the rise time of a signal is less than
or comparable to the time-of-flight delay of a line, it is necessary to consider the transmission …