Graphene nanoribbon as potential on-chip interconnect material—A review
A Hazra, S Basu - C, 2018 - mdpi.com
In recent years, on-chip interconnects have been considered as one of the most challenging
areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay …
areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay …
Mini-review: Modeling and performance analysis of nanocarbon interconnects
As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …
Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node
C Pan, P Raghavan, D Yakimets… - … on Electron Devices, 2015 - ieeexplore.ieee.org
For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure
is a strong candidate to sustain scaling according to Moore's Law. For the first time, the …
is a strong candidate to sustain scaling according to Moore's Law. For the first time, the …
Vertical graphene nanoribbon interconnects at the end of the roadmap
To solve electrical contact problem of horizontal multilayer graphene nanoribbon (GNR), a
vertical GNR (VGNR) interconnect scheme is proposed. Performance of the VGNR …
vertical GNR (VGNR) interconnect scheme is proposed. Performance of the VGNR …
Graphene-based interconnect exploration for large SRAM caches for ultrascaled technology nodes
Graphene-based interconnects are considered promising replacements for traditional
copper (Cu) interconnect due to their great electric properties. In this article, an interconnect …
copper (Cu) interconnect due to their great electric properties. In this article, an interconnect …
Reduced thickness interconnect model using GNR to avoid crosstalk effects
In this research article, we propose a reduced thickness multilayer graphene nanoribbon
(MLGNR) interconnect model to reduce crosstalk effects. The 10 * 10× higher current …
(MLGNR) interconnect model to reduce crosstalk effects. The 10 * 10× higher current …
Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method
S Bhattacharya, S Das, A Mukhopadhyay… - Journal of …, 2018 - Springer
A temperature-dependent delay optimization model for a multilayered graphene nanoribbon
(MLGNR) with top contact (TC-GNR), side contact (SC-GNR), and Cu-based nano …
(MLGNR) with top contact (TC-GNR), side contact (SC-GNR), and Cu-based nano …
On-chip interconnect trends, challenges and solutions: how to keep RC and reliability under control
Z Tőkei, I Ciofi, P Roussel, P Debacker… - … IEEE Symposium on …, 2016 - ieeexplore.ieee.org
On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under
control Page 1 On-chip interconnect trends, challenges and solutions: how to keep RC and …
control Page 1 On-chip interconnect trends, challenges and solutions: how to keep RC and …
Single-and multilayer graphene wires as alternative interconnects
In this work, we evaluate the material properties of graphene and assess the potential
application of graphene to replace copper wires in Back-End-Of-Line (BEOL) interconnects …
application of graphene to replace copper wires in Back-End-Of-Line (BEOL) interconnects …
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus
SRAM performance is highly dominated by interconnects as technology scales down
because of the significant parasitic resistance and capacitance in the interconnect. This …
because of the significant parasitic resistance and capacitance in the interconnect. This …