Applications and impacts of nanoscale thermal transport in electronics packaging
RJ Warzoha, AA Wilson… - Journal of …, 2021 - asmedigitalcollection.asme.org
This review introduces relevant nanoscale thermal transport processes that impact thermal
abatement in power electronics applications. Specifically, we highlight the importance of …
abatement in power electronics applications. Specifically, we highlight the importance of …
A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length
VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes
VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2022 - Elsevier
Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
Nanotube junctionless FET: proposal, design, and investigation
In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in
the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and …
the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and …
Insight into lateral band-to-band-tunneling in nanowire junctionless FETs
In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT)
component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET …
component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET …
Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2021 - Elsevier
In this paper, for the first time, we have investigated the DC and analog/RF performance
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications
N Vadthiya - ECS journal of solid state science and technology, 2021 - iopscience.iop.org
In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …
Spacer design guidelines for nanowire FETs from gate-induced drain leakage perspective
In this paper, we study for the first time the impact of the design of gate sidewall spacer on
the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) …
the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) …
Design of resistive load inverter and common source amplifier circuits using symmetric and asymmetric nanowire FETs
VB Sreenivasulu, NA Kumari, V Lokesh… - Journal of Electronic …, 2023 - Springer
In this paper, multi-channel nanowire (NW) performance is significantly improved by
symmetric and asymmetric spacer length optimization. Device performance metrics …
symmetric and asymmetric spacer length optimization. Device performance metrics …
Physical insights into the nature of gate-induced drain leakage in ultrashort channel nanowire FETs
In this paper, we demonstrate that the lateral band-to-band tunneling component of gate-
induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor …
induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor …