With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

Mask optimization has been a critical problem in the VLSI design flow due to the mismatch
between the lithography system and the continuously shrinking feature sizes. Optical …

With the rapid development of artificial intelligence and autonomous driving technology, the
demand for semiconductors is projected to rise substantially. However, the massive …

Detecting layout hotspots is one of the key problems in physical verification flow. Although
machine learning solutions show benefits over lithography simulation and pattern matching …

The design automation community has been actively exploring machine learning (ML) for
very-large-scale-integrated (VLSI) computer-aided design (CAD). Many studies have …

As the circuit feature size continuously shrinks down, hotspot detection has become a more
challenging problem in modern DFM flows. Developed deep learning techniques have …

Lithography simulation is one of the key steps in physical verification, enabled by the
substantial optical and resist models. A resist model bridges the aerial image simulation to …

Detecting defects in the inspection stage of semiconductor manufacturing process is a
crucial task to improve yield and productivity as well as wafer quality. Recent Advances in …

IR drop constraint is a fundamental requirement enforced in almost all chip designs.
However, its evaluation takes a long time, and mitigation techniques for fixing violations may …