In contemporary times, 3D integration is acknowledged as the most promising direction for
the development of the chip industry. The core technology behind 3D integration is through …

The large mismatches among the coefficients of thermal expansion (CTE) of the metal via,
insulator liner, and Si substrate of the through-silicon via (TSV) induce thermal stresses …

In this paper, Air-gaped Si interconnection for TSV interposer is presented, it's low stress due
to having similar coefficient of thermal expansion with Si interposer and is able to provide …

Driven by the need of reduced energy consumption in devices, 3D integration technology by
through silicon via (TSV) attracts increasing interests. However, high thermal stress is …

In this paper, a novel Si interposer for hermetical MEMS oriented System-in-Package
application is presented and it is a low stress, scalable platform with a stress releasing …

In this paper, a novel petaloid hollow Cu interconnection for interposer is presented, its
stress can be released by free ends face to hollow Cu interconnection center, and its …

To ensure maximum circuit reliability it is very important to estimate the circuit performance
and signal integrity in the circuit design phase. A full phase simulation for performance …

In this paper, a novel manufacturing scheme based on heat-depolymerizable material and
thermosetting material is proposed to achieve high performance through silicon vias (TSVs) …