Using non-trivial logic implications for trace buffer-based silicon debug

S Prabhakar, M Hsiao - 2009 Asian Test Symposium, 2009 - ieeexplore.ieee.org
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of
the circuit response during its functional, post-silicon operation. Due to the limited space of …

Fingerprint matching using minutia polygons

X Liang, T Asano - 18th International Conference on Pattern …, 2006 - ieeexplore.ieee.org
Fingerprint distortion changes both the geometric position and orientation of minutiae, and
leads to difficulties in establishing a match among multiple impressions acquired from the …

Multiplexed trace signal selection using non-trivial implication-based correlation

S Prabhakar, MS Hsiao - 2010 11th International Symposium …, 2010 - ieeexplore.ieee.org
Silicon debug with a trace buffer provides real-time visibility to the design under debug. It
traces a small subset of internal signals during its normal operation. The effectiveness of …

Evolving the quality of a model based test suite

U Farooq, CP Lam - 2009 International Conference on Software …, 2009 - ieeexplore.ieee.org
Redundant test cases in newly generated test suites often remain undetected until execution
and waste scarce project resources. In model-based testing, the testing process starts early …

Microprocessor system failures debug and fault isolation methodology

ME Amyeen, S Venkataraman… - 2009 International Test …, 2009 - ieeexplore.ieee.org
Diagnosis of functional failures can be used to debug design issues, isolate manufacturing
defects, and improve manufacturing yield. Automated failure analysis and rapid root-cause …

Trace buffer-based silicon debug with lossless compression

S Prabhakar, R Sethuram… - 2011 24th Internatioal …, 2011 - ieeexplore.ieee.org
The capacity of the available on-chip trace buffer is limited. To increase its capacity, we
propose real-time compression of the trace data via novel source transformation functions …

Lazy suspect-set computation: Fault diagnosis for deep electrical bugs

D Sengupta, FM de Paula, AJ Hu, A Veneris… - Proceedings of the …, 2012 - dl.acm.org
Current silicon test methods are highly effective at sensitizing and propagating most
electrical faults. Unfortunately, with ever increasing chip complexity and shorter time-to …

Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug

S Prabhakar - 2009 - vtechworks.lib.vt.edu
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of
the circuit response during its functional, post-silicon operation. Due to the limited space of …

Dataset development of GPU block using Scan Dump for Silicon Debug

KS Kulkarni, HVR Aradhya - 2021 6th International Conference …, 2021 - ieeexplore.ieee.org
In VLSI industry, Si debug is a crucial step of design flow before chipsets reach end users. It
is a challenging phase, especially for complex systems like Microcontrollers and Processors …

Exploiting advanced fault localization methods for yield & reliability learning on SoCs

D Appello - 2009 International Symposium on VLSI Design …, 2009 - ieeexplore.ieee.org
Exploiting advanced fault localization methods for yield & reliability learning on
SoCs Page 1 Exploiting Advanced Fault Localization Methods for Yield & Reliability …