An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

S Sarkar, S Banerjee - Microelectronics journal, 2014 - Elsevier
In this work an 8-bit DAC is presented which uses a new segmented architecture, where
distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The …

A 12.8-ns-latency DDFS MMIC with frequency, phase, and amplitude modulations in 65-nm CMOS

AM Alonso, M Miyahara… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper describes a digital-mapping direct digital frequency synthesizer having a tuning
and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic …

A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in 0.13 μm CMOS

X Guo, D Wu, L Zhou, H Liu, J Wu, X Liu - Analog Integrated Circuits and …, 2018 - Springer
A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a
maximum operating frequency of 2 GHz is presented. The proposed ROM-based design is …

Phase to Amplitude Converter

J Zhang, R Zhang, G Li - High-Speed and High-Performance Direct Digital …, 2022 - Springer
Phase to amplitude converter is one of the key module of DDS. As shown in Fig. 2.1, a
typical DDS system consists of a phase accumulator, a phase to amplitude converter and a …

A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme

S Sarkar, S Banerjee - 2015 International Conference on …, 2015 - ieeexplore.ieee.org
The effect of bias node voltage fluctuations on the performance of the current steering (CS)
DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been …

Mixed-Signal Integrated Circuits for Interference Tolerance in Wireless Receivers and Fast Frequency Hopping

S Subramanian - 2017 - search.proquest.com
Modern wireless communication systems require low power integrated circuit
implementations of radio receivers that simultaneously offer programmability and …