Low-power modified shift-add multiplier design using parallel prefix adder

R Pinto, K Shama - Journal of Circuits, Systems and Computers, 2019 - World Scientific
Multipliers are the building blocks of every digital signal processor (DSP). The performance
of any digital system is dependent on the adder design and to a large extent on the multiplier …

Design an area efficient kogge stone adder using pass transistor logic

S Daphni, KSV Grace - 2021 Third international conference on …, 2021 - ieeexplore.ieee.org
In recent technologies of Electronics applications, Adder is an important source of any
devices such as DSP, VLSI applications. For which, many electronics application devices …

[PDF][PDF] Implementation of low power and memory efficient 2D FIR filter architecture

VK Odugu, CV Narasimhulu… - International Journal of …, 2019 - researchgate.net
 Abstract: A memory efficient design is analyzed to derive a low power-area-delay two
dimensional (2D) Finite Impulse Response (FIR) filter architecture. The parallel processing …

[PDF][PDF] FPGA synthesis and validation of parallel prefix adders

QA Al-Haija, MM Asad, I Marouf… - Acta Electronica …, 2019 - researchgate.net
The main objective of this paper is to attain the best achievable time delay reduction with
better performance (ie frequency) running on FPGA platforms and prove their applicability in …

Design and analysis of low power and high speed FinFET based hybrid full adder/subtractor circuit (FHAS)

E Ramkumar, D Gracin, P Rajkamal… - … on Smart Electronic …, 2020 - ieeexplore.ieee.org
In this paper, two novel hybrid adder designs, namely, FHAS-1 and FHAS-2 have been
proposed. These designs are designed using multiplexor, XOR and XNOR gates and they …

Qualitative and quantitative analysis of parallel-prefix adders

S Janwadkar, R Dhavse - Advances in VLSI and Embedded Systems …, 2020 - Springer
Binary adders are one of the most recurrent architectures in digital VLSI design, and the
choice of adder architecture can boost or bust the overall performance of the design. Parallel …

Synthesis of parallel adders from if-decision diagrams

AA Prihozhy - 2020 - rep.bntu.by
Addition is one of the timing critical operations in most of modern processing units. For
decades, extensive research has been done devoted to designing higher speed and less …

Fast large integer modular addition in GF (p) using novel attribute-based representation

B Alhazmi, F Gebali - IEEE Access, 2019 - ieeexplore.ieee.org
Addition is an essential operation in all cryptographic algorithms. Higher levels of security
require larger key sizes and this becomes a limiting factor in GF (p) using large integers …

A comparative performance evaluation for hybrid parallel adders in terms of delay, area, power, and energy Gecikme, alan, güç ve enerji açısından hibrit paralel …

İ Avcı, C Özarpa, M AYDIN - … of the Faculty of Engineering and …, 2023 - avesis.istanbul.edu.tr
In the era of developing technology, faster applications in modern electronic systems
increase the demands for less energy consumption, area, power, and delay. This research …

Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi

İ Avcı, C Özarpa, MA Aydın - Gazi Üniversitesi Mühendislik Mimarlık …, 2023 - dergipark.org.tr
Gelişen teknoloji çağında modern elektronik sistemlerde daha hızlı uygulamalar daha az
enerji tüketimi, alan, güç ve gecikme taleplerini artırmaktadır. Bu araştırma çalışması, paralel …