Neuromorphic computing has emerged as one of the most promising paradigms to
overcome the limitations of von Neumann architecture of conventional digital processors …

The proliferation of data has facilitated global accessibility, which demands escalating
amounts of power for data storage and processing purposes. In recent years, there has been …

We propose a CMOS Analog Vector-Matrix Multiplier for Deep Neural Networks,
implemented in a standard single-poly 180 nm CMOS technology. The learning weights are …

An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a
spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like …

A hardware-based neural network that enables on-chip training using a thin-film transistor-
type AND flash memory array architecture is designed. The synaptic device constituting the …

In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap
flash (CTF) synapse array (synapses) and CMOS integrate-and-fire (IF) neurons is …

This article and its part II demonstrate the possibility to operate a mainstream NOR Flash
memory array as an artificial synaptic array learning without external supervision according …

Recently, analog in-memory computing (IMC) systems exhibit the considerable potential to
break through the inherent high computational latency and energy cost of Von Neumann's …

Artificial intelligence (AI) has recently received significant attention as a key enabler for
future 5G-and-beyond terrestrial wireless networks. The applications of AI to satellite …

With the rapid development of machine learning, the demand for high-efficient computing
becomes more and more urgent. To break the bottleneck of the traditional Von Neumann …