IMesh, the tile processor architecture's on-chip interconnection network, connects the
multicore processor's tiles with five 2D mesh networks, each specialized for a different use …

With the trend towards increasing number of cores in chip multiprocessors, the on-chip
interconnect that connects the cores needs to scale efficiently. In this work, we propose the …

Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in
chip multiprocessors and system-on-chip designs. Existing interconnection networks use …

This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …

As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors,
networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric …

With the increasing miniaturization of transistors, wire delays are becoming a dominant
factor in microprocessor performance. To address this issue, a number of emerging …

Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency
for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-to-all …

This book targets engineers and researchers familiar with basic computer architecture
concepts who are interested in learning about on-chip networks. This work is designed to be …

Minimizing latency and maximizing throughput are important goals in the design of routing
algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a) …

Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has
evolved from proprietary busses to networked architectures. A similar evolution is occurring …