[图书][B] Metrology and Diagnostic Techniques for Nanoelectronics

Z Ma, DG Seiler - 2017 - taylorfrancis.com
Nanoelectronics is changing the way the world communicates, and is transforming our daily
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …

Modeling and characterization of annealing-induced Cu protrusion of TSVs with polyimide liner considering diffusion creep behavior

B Yang, Y Ding, Z Cheng, A Ren, L Xiao… - … on Electron Devices, 2022 - ieeexplore.ieee.org
Polymer liner has been used in through-silicon-vias (TSVs) for smaller parasitic capacitance
and better thermo-mechanical performance. For the application in heterogeneous integrated …

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD

V Jousseaume, C Guerin, K Ichiki… - … Applied Materials & …, 2024 - ACS Publications
In microelectronics, one of the main 3D integration strategies consists of vertically stacking
and electrically connecting various functional chips using through-silicon vias (TSVs). For …

Elimination of scallop-induced stress fluctuation on through-silicon-vias (TSVs) by employing polyimide liner

C Xue, Z Cheng, Z Chen, Y Yan, Z Cai… - IEEE transactions on …, 2018 - ieeexplore.ieee.org
3-D modeling of through-silicon-via (TSV) with sidewall scallops, combined with an element
birth and death technique, is explored in finite-element analysis (FEA) in this paper to …

Innovative polyimide liner deposition method for high-aspect-ratio and high-density through-silicon-vias (TSVs)

Y Ding, M Xiong, Y Yan, S Wang, Q Chen… - Microelectronic …, 2016 - Elsevier
Abstract In three-dimensional (3D) integration, liner deposition technique with excellent step
coverage is a challenge to realize through-silicon-vias (TSVs), especially for TSVs with high …

TSV and Cu-Cu direct bond wafer and package-level reliability

K Hummler, B Sapp, JR Lloyd, S Kruger… - 2013 IEEE 63rd …, 2013 - ieeexplore.ieee.org
A comprehensive study of reliability failure modes in an advanced through-silicon via (TSV)
mid process flow is presented in Part I of this paper. This is the first time unique TSV mid …

A Novel Double-Sided Etching and Electroplating Fabrication Scheme for Coaxial Through-Silicon-Vias in 3-D Integration

Z Chen, X Chen, H Wang, Z Cai… - … on Electron Devices, 2024 - ieeexplore.ieee.org
Compared to conventional through-silicon-via (TSV) technology, coaxial TSVs can provide
better radio frequency (RF) transmission performance in terms of reduced transmission loss …

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

YY Yan, M Xiong, B Liu, YT Ding, ZM Chen - Science China Technological …, 2016 - Springer
Low-k and high aspect ratio blind through-silicon-vias (TSVs) to be applied in “via-
last/backside via” 3-D integration paradigm were fabricated with polyimide dielectric liners …

[HTML][HTML] Elastic and elastic-plastic analysis of multilayer thin films filled with heterogeneous materials

J Luo, Y Sun, B Wang, Z Jin, S Yang, Y Wang, G Ding - AIP Advances, 2018 - pubs.aip.org
Due to the mismatch between the coefficients of thermal expansion (CTE) of two adjacent
films, the residual stress was growing up during thermal cycling. The aim of this work is to …

Thermal stresses of TSVs with silicon post conductors and polymer insulators

Q Ma, K Wu, Z Wang - IEEE Transactions on Components …, 2016 - ieeexplore.ieee.org
Due to the advantages of ease of fabrication, low cost, and potential high reliability, through-
silicon-vias (TSVs) using low-resistivity silicon posts as conductors and circular polymer …