Bi-modal dram cache: Improving hit rate, hit latency and bandwidth

N Gulur, M Mehendale, R Manikantan… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
In this paper, we present Bi-Modal Cache-a flexible stacked DRAM cache organization
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …

Optical cache memory peripheral circuitry: Row and column address selectors for optical static RAM banks

T Alexoudi, S Papaioannou… - Journal of lightwave …, 2013 - ieeexplore.ieee.org
We demonstrate WDM-enabled all-passive optical row and column address selector
(RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical …

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context

E Guthmuller, I Miro-Panades… - 2013 IFIP/IEEE 21st …, 2013 - ieeexplore.ieee.org
New fine-grained 3D cache architectures have been recently proposed to embed more
memory on-chip and thus reduce off-chip memory accesses. These 3D architectures provide …

Bi-modal dram cache: A scalable and effective die-stacked dram cache

N Gulur, M Mehendale, R Manikantan… - Proceedings of the 47th …, 2014 - dl.acm.org
In this paper, we present Bi-Modal Cache-a flexible stacked DRAM cache organization
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …

3D integration for power-efficient computing

D Dutoit, E Guthmuller… - 2013 Design, Automation …, 2013 - ieeexplore.ieee.org
3D stacking is currently seen as a breakthrough technology for improving bandwidth and
energy efficiency in multi-core architectures. The expectation is to solve major issues such …

A stackable LTE chip for cost-effective 3D systems

W Lafi, D Lattard, A Jerraya - IPSJ Transactions on System and LSI …, 2012 - jstage.jst.go.jp
To address the problem of prohibitive cost of advanced fabrication technologies, one
solution consists in reusing masks to address a wide range of ICs. This could be achieved …

[图书][B] Optimizing the internal microarchitecture and ISA of a traveling thread pim system

PA La Fratta - 2011 - search.proquest.com
Heterogeneity, multiple on-chip processing elements, multithreading, intelligent caching
mechanisms, and compiler-assisted thread-level speculation are a few of the features of …

An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology

HY Lim, GH Park - IEICE Electronics Express, 2013 - jstage.jst.go.jp
Three-dimensional integration circuits (3-D ICs) technology provides various opportunities
for new computer system architectures. Data prefetching, which can utilize the abundant …

Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology

HY Lim, GH Park - 2011 IEEE International 3D Systems …, 2012 - ieeexplore.ieee.org
Three-dimensional (3-D) integration technology dramatically increases the memory
bandwidth by stacking memory directly on the top of a processor. This paper proposes a …

Dynamic Bandwidth Allocation for an OFDMA based RF Network-on-Chip

E Unlu - 2016 - hal.science
With increasing silicon manufacturing capabilities, it is expected that chip multiprocessors
(CMPs) with thousands of cores will be ready before 2030. With increasing number of cores …