Reconfigurable computing architectures
Reconfigurable architectures can bring unique capabilities to computational tasks. They
offer the performance and energy efficiency of hardware with the flexibility of software. In …
offer the performance and energy efficiency of hardware with the flexibility of software. In …
[图书][B] Reconfigurable computing: the theory and practice of FPGA-based computation
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …
between the separate worlds of hardware and software design—the key feature of …
Packet switched vs. time multiplexed FPGA overlay networks
Dedicated, spatially configured FPGA interconnect is efficient for applications that require
high throughput connections between processing elements (PEs) but with a limited degree …
high throughput connections between processing elements (PEs) but with a limited degree …
Architectural exploration of the ADRES coarse-grained reconfigurable array
F Bouwens, M Berekovic, A Kanstein… - … : Architectures, Tools and …, 2007 - Springer
Reconfigurable computational architectures are envisioned to deliver power efficient, high
performance, flexible platforms for embedded systems design. The coarse-grained …
performance, flexible platforms for embedded systems design. The coarse-grained …
FPGA optimized packet-switched NoC using split and merge primitives
Y Huan, A DeHon - 2012 International Conference on Field …, 2012 - ieeexplore.ieee.org
Due to their different cost structures, the architecture of switches for an FPGA packet-
switched Network-on-a-Chip (NoC) should differ from their ASIC counterparts. The …
switched Network-on-a-Chip (NoC) should differ from their ASIC counterparts. The …
PLD: Fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development
FPGA-based accelerators are demonstrating significant absolute performance and energy
efficiency compared with general-purpose CPUs. While FPGA computations can now be …
efficiency compared with general-purpose CPUs. While FPGA computations can now be …
Parallel hardware hypervisor for virtualizing application-specific supercomputers
7. B-1 (P1) sends message to Bo (not mapped) Cache miss handled by owner P3 containing
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …
Reducing FPGA compile time with separate compilation for FPGA building blocks
Today's FPGA compilation is slow because it compiles and co-optimizes the entire design in
one monolithic mapping flow. This achieves high quality results but also means a long edit …
one monolithic mapping flow. This achieves high quality results but also means a long edit …
Topology adaptive network-on-chip design and implementation
TA Bartic, JY Mignolet, V Nollet, T Marescaux… - … -Computers and Digital …, 2005 - IET
Network-on-chip designs promise to offer considerable advantages over the traditional bus-
based designs in solving the numerous technological, economic and productivity problems …
based designs in solving the numerous technological, economic and productivity problems …
Stream computations organized for reconfigurable execution
Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level
resource control traditionally associated with hardware implementations, along with the …
resource control traditionally associated with hardware implementations, along with the …