一种SRAM 型FPGA 互连资源的位流码配置方法

李智华, 黄娟, 李威, 杨立群, 黄俊英… - Journal of terahertz …, 2016 - opticsjournal.net
摘要针对静态随机存取存储器(SRAM) 型现场可编程门阵列(FPGA) 位流码配置问题,
提出一种自动配置互连资源的方法. 该方法从描述FPGA 结构的行为级Verilog 文件中 …

[图书][B] Ordinary Differential Equation Multi-Domain Models of MEMS Structures

CJ Childs - 2023 - search.proquest.com
Modeling is a pivotal part of any modern design process. The ability to accurately predict
designs before building cuts down on development costs leading to faster development …

[PDF][PDF] Top-Level Layout Design of Solid-State Energy Meter

M Andrejević, M Savić, M Nikolić… - Proc. XLVIII ETRAN …, 2004 - leda.elfak.ni.ac.rs
This paper presents top-level layout design of solid-state energy meter chip. The chip is
mixed-signal, consisting of analog and digital part. The layout design flows for analog and …

[PDF][PDF] Experience in Using Open Command Environment for Analysis in Education

D Mirković, P Petković, V Litovski - leda.elfak.ni.ac.rs
Command Environment for Analysis (OCEAN) for teaching IC design at University of Niš. IC
design requires a lot of repetitive analysis needed to get better insight into possibilities of a …

[PDF][PDF] ASCEND-FREEPDK45: PROJETO E IMPLEMENTAÇÃO DE UMA BIBLIOTECA DE CÉLULAS ABERTA PARA CIRCUITOS ASSÍNCRONOS

CH MENEZES - 2015 - inf.pucrs.br
RESUMO A análise do estado da arte em circuitos assíncronos revela a carência de
recursos de apoio ao projeto. Dentre os recursos que fazem falta ressalta-se a escassez de …

[PDF][PDF] Verification of Digital System Test Patterns using a VHDL Simulator

M Sokolović, M Zwolinski - ELEKTRONIKA ELECTRONICS - academia.edu
In this paper an approach for test pattern verification for a digital system-on-chip is proposed.
It is based on digital system simulation using a standard VHDL simulator. The approach is …

[PDF][PDF] Generation of Digital System Test Patterns Based on VHDL Simulations

M SOKOLOVIĆ, A KUIPER - 160.99.12.1
In this paper an approach for test pattern generation and verification for a digital system-on-
chip is proposed. It is based on digital system simulation using a standard VHDL simulator …

[PDF][PDF] DOKUMENTACIJA U PROJEKTOVANJU INTEGRISANOG MERAČA POTROŠNJE ELEKTRIČNE ENERGIJE–IMPEG

MA Dimitrijević - Proc. XLVIII ETRAN Conference, 2004 - leda.elfak.ni.ac.rs
Integrisani merač potrošnje električne energije–IMPEG je integrisano kolo namenjeno za
bidirekciono merenje aktivne i reaktivne energije u trofaznim sistemima. Osnovna namena …