Validation of side-channel models via observation refinement

P Buiras, H Nemati, A Lindner… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Observational models enable the analysis of information flow properties against side
channels. Relational testing has been used to validate the soundness of these models by …

Validation of abstract side-channel models for computer architectures

H Nemati, P Buiras, A Lindner, R Guanciale… - … Aided Verification: 32nd …, 2020 - Springer
Observational models make tractable the analysis of information flow properties by providing
an abstraction of side channels. We introduce a methodology and a tool, Scam-V, to validate …

[HTML][HTML] On the Analysis of Coverage Feedback in a Fuzzing Proprietary System

D Jang, J Kim, J Kim, W Im, M Jeong, B Choi, C Kil - Applied Sciences, 2024 - mdpi.com
Coverage feedback is one of the key mechanisms for improving the effectiveness of fuzzers
by measuring and comparing the executed code regions while processing input data. In …

Parallelized sequential composition and hardware weak memory models

RJ Colvin - International Conference on Software Engineering and …, 2021 - Springer
Since the 1960s processors have, for efficiency, sometimes executed instructions out of
program order, provided that the (sequential) semantics is preserved. On uniprocessor …

An isabelle/hol formalisation of the SPARC instruction set architecture and the TSO memory model

Z Hóu, D Sanan, A Tiu, Y Liu, KC Hoa… - Journal of Automated …, 2021 - Springer
The SPARC instruction set architecture (ISA) has been used in various processors in
workstations, embedded systems, and in mission-critical industries such as aviation and …

Real-time system modeling and verification through labeled transition system analyzer

Y Yang, Q Zu, W Ke, M Zhang, X Li - IEEE Access, 2019 - ieeexplore.ieee.org
Model checking as a computer-assisted verification method is widely used in many fields to
verify whether a design model satisfies the requirements specifications of the target system …

[HTML][HTML] Formalizing SPARCv8 instruction set architecture in Coq

J Wang, M Fu, L Qiao, X Feng - Science of Computer Programming, 2020 - Elsevier
The SPARCv8 instruction set architecture (ISA) has been widely used in various processors
for workstations, embedded systems, and space missions. In order to formally verify the …

Parallelized sequential composition, pipelines, and hardware weak memory models

RJ Colvin - arXiv preprint arXiv:2105.02444, 2021 - arxiv.org
Since the introduction of the CDC 6600 in 1965 and itsscoreboarding'technique processors
have not (necessarily) executed instructions in program order. Programmers of high-level …

Formal verification of digital circuits using simulator with mathematical foundation

W Khan, B Azam, N Shahid… - Applied mechanics …, 2019 - Trans Tech Publ
To ease hardware design process, circuits are normally designed in description languages
such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive …

An executable formal model of the vhdl in isabelle/hol

W Khan, Z Hou, D Sanan, J Nebhen, Y Liu… - arXiv preprint arXiv …, 2022 - arxiv.org
In the hardware design process, hardware components are usually described in a hardware
description language. Most of the hardware description languages, such as Verilog and …