A power-efficient pipeline based clock gating FIFO for a dual ported memory array.

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A power-efficient pipeline based clock gating FIFO for a dual ported memory array.

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Performance Evaluation of Adder Architectures for Vedic Multiplier Implementation

S Dhanasekar, AM Anitha, M Karunaya… - 2023 4th IEEE …, 2023 - ieeexplore.ieee.org

Performance evaluation of adder architectures for Vedic multiplier implementation is
introduced in this article. The purpose is to evaluate and analyze various adder architectures …

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A power-efficient pipeline based clock gating FIFO for a dual ported memory array.

Performance Evaluation of Adder Architectures for Vedic Multiplier Implementation

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