Hardware security has recently re-surfaced as a first-order concern to the confidentiality
protections of computing systems. Meltdown and Spectre introduced a new class of …

The high access latency of DRAM continues to be a performance challenge for
contemporary microprocessor systems. Prefetching is a well-established technique to …

High performance microprocessors require high levels of instruction supply. Branch
prediction has been the most important driver of this for nearly 30 years. Unfortunately …

Memory-bound stalls account for a significant portion of CPU cycles in datacenter
workloads, which makes harvesting them to execute other useful work highly valuable …

Runahead execution improves processor performance by accurately prefetching long-
latency memory accesses. When a long-latency load causes the instruction window to fill up …

The memory wall places a significant limit on performance for many modern workloads.
These applications feature complex chains of dependent, indirect memory accesses, which …

Modern processors employ large structures (IQ, LSQ, register file, etc.) to expose instruction-
level parallelism (ILP) and memory-level parallelism (MLP). These resources are typically …

Superscalar out-of-order cores deliver high performance at the cost of increased complexity
and power budget. In-order cores, in contrast, are less complex and have a smaller power …

Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level
cache access latencies. While out-of-order (OoO) cores, and techniques building on them …

Flexible instruction scheduling is essential for performance in out-of-order processors. This
is typically achieved by using CAM-based Instruction Queues (IQs) that provide complete …